Re: [PATCH] target/ppc: Do not check for LPCR[HAIL] on power10_v1.0 CPUs

[Nicholas Piggin <npiggin@gmail.com>]

Excerpts from Cédric Le Goater's message of May 4, 2021 7:59 pm:
> The LPCR[HAIL] bit only applies to POWER10 DD2 CPUs. On POWER10 DD1,
> the ail value should be extracted using the LPCR_AIL mask like on P9.
> 
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Thanks for this, my oversight for not realising the P10 CPU is DD1 
(which doesn't have HAIL).

I wonder if it could just use the POWER9 excp_model?

> ---
>  target/ppc/excp_helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index c0605f84d70f..ba18444f5d1e 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -198,6 +198,7 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
>                                        target_ulong *vector)
>  {
>  #if defined(TARGET_PPC64)
> +    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>      CPUPPCState *env = &cpu->env;
>      bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1);
>      bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB);
> @@ -240,7 +241,7 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
>              return;
>          }
>  
> -        if (*new_msr & MSR_HVB) {
> +        if (*new_msr & MSR_HVB && pcc->lpcr_mask & LPCR_HAIL) {
>              if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) {
>                  /* HV interrupts depend on LPCR[HAIL] */
>                  return;
> -- 
> 2.26.3
> 
>