From: Ye Li <ye.li@nxp.com>
To: Gaurav Jain <gaurav.jain@nxp.com>,
"u-boot@lists.denx.de" <u-boot@lists.denx.de>
Cc: "olteanv@gmail.com" <olteanv@gmail.com>,
Priyanka Jain <priyanka.jain@nxp.com>,
Pankaj Gupta <pankaj.gupta@nxp.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
Silvano Di Ninno <silvano.dininno@nxp.com>,
"sjg@chromium.org" <sjg@chromium.org>, Ji Luo <ji.luo@nxp.com>,
"festevam@gmail.com" <festevam@gmail.com>,
dl-uboot-imx <uboot-imx@nxp.com>,
Shengzhou Liu <shengzhou.liu@nxp.com>,
Rajesh Bhagat <rajesh.bhagat@nxp.com>,
Franck Lenormand <franck.lenormand@nxp.com>,
Varun Sethi <V.Sethi@nxp.com>, Alison Wang <alison.wang@nxp.com>,
Peng Fan <peng.fan@nxp.com>, Wasim Khan <wasim.khan@nxp.com>,
Pramod Kumar <pramod.kumar_1@nxp.com>,
"sbabic@denx.de" <sbabic@denx.de>,
Horia Geanta <horia.geanta@nxp.com>,
Andy Tang <andy.tang@nxp.com>,
Sahil Malhotra <sahil.malhotra@nxp.com>,
Adrian Alonso <adrian.alonso@nxp.com>
Subject: Re: [PATCH v2 08/15] i.MX8: Add crypto node in device tree
Date: Fri, 10 Sep 2021 09:39:55 +0000 [thread overview]
Message-ID: <1631266779.43076.49.camel@nxp.com> (raw)
In-Reply-To: <20210903070319.13484-9-gaurav.jain@nxp.com>
On Fri, 2021-09-03 at 12:33 +0530, Gaurav Jain wrote:
> i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
>
> disabled use of JR1 in SPL and uboot, as JR1 is reserved
> for SECO FW.
>
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Best regards,
Ye Li
> ---
> arch/arm/dts/fsl-imx8dx.dtsi | 61
> +++++++++++++++++++++++-
> arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 ++++++++++++-
> arch/arm/dts/fsl-imx8qm.dtsi | 61
> +++++++++++++++++++++++-
> arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 ++++++++++++-
> 4 files changed, 186 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-
> imx8dx.dtsi
> index 7d95cf0b7d..63a56699b5 100644
> --- a/arch/arm/dts/fsl-imx8dx.dtsi
> +++ b/arch/arm/dts/fsl-imx8dx.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -261,6 +261,30 @@
> power-domains = <&pd_dma>;
> };
> };
> +
> + pd_caam: PD_CAAM {
> + compatible = "nxp,imx8-pd";
> + reg = <SC_R_NONE>;
> + #power-domain-cells = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pd_caam_jr1: PD_CAAM_JR1 {
> + reg = <SC_R_CAAM_JR1>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_caam>;
> + };
> + pd_caam_jr2: PD_CAAM_JR2 {
> + reg = <SC_R_CAAM_JR2>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_caam>;
> + };
> + pd_caam_jr3: PD_CAAM_JR3 {
> + reg = <SC_R_CAAM_JR3>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_caam>;
> + };
> + };
> };
>
> i2c0: i2c@5a800000 {
> @@ -609,6 +633,41 @@
> };
> };
> };
> +
> + crypto: caam@0x31400000 {
> + compatible = "fsl,sec-v4.0";
> + reg = <0 0x31400000 0 0x400000>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x31400000 0x400000>;
> + fsl,first-jr-index = <2>;
> + fsl,sec-era = <9>;
> +
> + sec_jr1: jr1@0x20000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x20000 0x1000>;
> + interrupts = <GIC_SPI 452
> IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd_caam_jr1>;
> + status = "disabled";
> + };
> +
> + sec_jr2: jr2@30000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x30000 0x1000>;
> + interrupts = <GIC_SPI 453
> IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd_caam_jr2>;
> + status = "okay";
> + };
> +
> + sec_jr3: jr3@40000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x40000 0x1000>;
> + interrupts = <GIC_SPI 454
> IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd_caam_jr3>;
> + status = "okay";
> + };
> + };
> };
>
> &A35_0 {
> diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> index 9e0d264b71..a95209e141 100644
> --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> &{/imx8qm-pm} {
> @@ -80,6 +80,22 @@
> u-boot,dm-spl;
> };
>
> +&pd_caam {
> + u-boot,dm-spl;
> +};
> +
> +&pd_caam_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&pd_caam_jr2 {
> + u-boot,dm-spl;
> +};
> +
> +&pd_caam_jr3 {
> + u-boot,dm-spl;
> +};
> +
> &gpio0 {
> u-boot,dm-spl;
> };
> @@ -126,3 +142,19 @@
> sd-uhs-sdr104;
> sd-uhs-ddr50;
> };
> +
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr3 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-
> imx8qm.dtsi
> index 88aeaf65b3..517fb13cad 100644
> --- a/arch/arm/dts/fsl-imx8qm.dtsi
> +++ b/arch/arm/dts/fsl-imx8qm.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -235,6 +235,30 @@
> wakeup-irq = <349>;
> };
> };
> +
> + pd_caam: PD_CAAM {
> + compatible = "nxp,imx8-pd";
> + reg = <SC_R_NONE>;
> + #power-domain-cells = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pd_caam_jr1: PD_CAAM_JR1 {
> + reg = <SC_R_CAAM_JR1>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_caam>;
> + };
> + pd_caam_jr2: PD_CAAM_JR2 {
> + reg = <SC_R_CAAM_JR2>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_caam>;
> + };
> + pd_caam_jr3: PD_CAAM_JR3 {
> + reg = <SC_R_CAAM_JR3>;
> + #power-domain-cells = <0>;
> + power-domains = <&pd_caam>;
> + };
> + };
> };
>
> i2c0: i2c@5a800000 {
> @@ -556,6 +580,41 @@
> power-domains = <&pd_conn_enet1>;
> status = "disabled";
> };
> +
> + crypto: caam@0x31400000 {
> + compatible = "fsl,sec-v4.0";
> + reg = <0 0x31400000 0 0x400000>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x31400000 0x400000>;
> + fsl,first-jr-index = <2>;
> + fsl,sec-era = <9>;
> +
> + sec_jr1: jr1@0x20000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x20000 0x1000>;
> + interrupts = <GIC_SPI 452
> IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd_caam_jr1>;
> + status = "disabled";
> + };
> +
> + sec_jr2: jr2@30000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x30000 0x1000>;
> + interrupts = <GIC_SPI 453
> IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd_caam_jr2>;
> + status = "okay";
> + };
> +
> + sec_jr3: jr3@40000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x40000 0x1000>;
> + interrupts = <GIC_SPI 454
> IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd_caam_jr3>;
> + status = "okay";
> + };
> + };
> };
>
> &A53_0 {
> diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> index 701af4434d..ae037c7550 100644
> --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> */
>
> &{/imx8qx-pm} {
> @@ -80,6 +80,22 @@
> u-boot,dm-spl;
> };
>
> +&pd_caam {
> + u-boot,dm-spl;
> +};
> +
> +&pd_caam_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&pd_caam_jr2 {
> + u-boot,dm-spl;
> +};
> +
> +&pd_caam_jr3 {
> + u-boot,dm-spl;
> +};
> +
> &gpio0 {
> u-boot,dm-spl;
> };
> @@ -126,3 +142,19 @@
> sd-uhs-sdr104;
> sd-uhs-ddr50;
> };
> +
> +&crypto {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr1 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr2 {
> + u-boot,dm-spl;
> +};
> +
> +&sec_jr3 {
> + u-boot,dm-spl;
> +};
next prev parent reply other threads:[~2021-09-10 9:40 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 7:03 [PATCH v2 00/15] Add CAAM driver model support Gaurav Jain
2021-09-03 7:03 ` [PATCH v2 01/15] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2021-09-10 10:01 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 02/15] crypto/fsl: Add CAAM support for bkek, random number generation Gaurav Jain
2021-09-10 9:46 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 03/15] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
2021-09-10 9:03 ` Ye Li
2021-09-10 14:46 ` Tim Harvey
2021-09-13 4:55 ` [EXT] " Gaurav Jain
2021-09-23 22:40 ` Tim Harvey
2021-09-28 5:20 ` Gaurav Jain
2021-09-03 7:03 ` [PATCH v2 04/15] crypto/fsl: i.MX8M: Enable Job ring driver model in SPL and U-Boot Gaurav Jain
2021-09-10 9:04 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 05/15] i.MX6: Enable Job ring driver model in U-Boot Gaurav Jain
2021-09-10 9:20 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 06/15] i.MX7: " Gaurav Jain
2021-09-10 9:36 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 07/15] i.MX7ULP: " Gaurav Jain
2021-09-10 9:36 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 08/15] i.MX8: Add crypto node in device tree Gaurav Jain
2021-09-10 9:39 ` Ye Li [this message]
2021-09-03 7:03 ` [PATCH v2 09/15] crypto/fsl: i.MX8: Enable Job ring driver model in SPL and U-Boot Gaurav Jain
2021-09-10 9:43 ` Ye Li
2021-09-03 7:03 ` [PATCH v2 10/15] crypto/fsl: Fix kick_trng Gaurav Jain
2021-09-03 7:03 ` [PATCH v2 11/15] Layerscape: Add crypto node in device tree Gaurav Jain
2021-09-13 7:08 ` Priyanka Jain (OSS)
2021-09-03 7:03 ` [PATCH v2 12/15] Layerscape: Enable Job ring driver model in U-Boot Gaurav Jain
2021-09-13 7:10 ` Priyanka Jain (OSS)
2021-09-03 7:03 ` [PATCH v2 13/15] PPC: Add crypto node in device tree Gaurav Jain
2021-09-13 7:10 ` Priyanka Jain (OSS)
2021-09-03 7:03 ` [PATCH v2 14/15] PPC: Enable Job ring driver model in U-Boot Gaurav Jain
2021-09-13 7:13 ` Priyanka Jain (OSS)
2021-09-03 7:03 ` [PATCH v2 15/15] update CAAM MAINTAINER Gaurav Jain
2021-09-23 23:01 ` [PATCH v2 00/15] Add CAAM driver model support Tim Harvey
2021-09-28 5:39 ` [EXT] " Gaurav Jain
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