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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id c3-20020a2e9d83000000b0029352fc39fbsm700236ljj.63.2023.03.12.11.10.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:10:22 -0700 (PDT) Message-Id: <1678644516.665314-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 0/3] mmc: dw_mmc: fix DW MMC cores with 32-bit bus on 64-bit Linux systems To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org DesignWare MMC cores have a configurable data bus width of either 16, 32, or 64 bytes. It is possible, and some vendors actually do it, to ship a DW MMC core configured for 32-bit data bus within a 64-bit SoC. In this case the kernel will attempt 64-bit (readq) accesses to certain 64-bit MMIO registers, while the core will expect pairs of 32-bit accesses. It seems that currently the only register for which the kernel performs 64-bit accesses is the FIFO. The symptom is that the DW MMC core never receives a read on the second half of the register, does not register the datum as being read, and thus not advancing its internal FIFO pointer, breaking further reads. It also seems that this FIFO is only used for small (less than 16 bytes) transfers, which probably means that only some SDIO cards are affected. Changelog: v5: - rename "samsung,exynos78xx-dw-mshc" to "samsung,exynos7885-dw-mshc" - rename "samsung,exynos78xx-dw-mshc" to "samsung,exynos7885-dw-mshc" v4: - split dt-bindings and dts update into separate commits - add an explanation why it'ss necessary to change the compatible string v3: - removed "fifo-access-32bit" devicetree property - added "samsung,exynos78xx-dw-mshc" compatible string - added "samsung,exynos78xx-dw-mshc-smu" compatible string v2: - added commit messages v1: - added "fifo-access-32bit" devicetree property - added DW_MMC_QUIRK_FIFO64_32 - added new dw_mci_{pull,push}_data* variants (...-data64_32) Sergey Lisov (3): dt-bindings: exynos-dw-mshc-common: add exynos7885 variants mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO arm64: dts: exynos: fix wrong mmc compatible in exynos7885.dtsi .../bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 + arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- drivers/mmc/host/dw_mmc-exynos.c | 43 +++++- drivers/mmc/host/dw_mmc.c | 122 +++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 5 files changed, 167 insertions(+), 4 deletions(-) -- 2.38.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85F02C6FD19 for ; Sun, 12 Mar 2023 18:11:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Date:From: Message-Id:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=oTbiuNL6sGzO+sgGck0p9V1OhrMeCDnAG1O7LlTtMpE=; b=JeM3RQCiD3PDVE BMRPmt1EnBEaeMwXclphr/rvoIomFoaGxIf9q6dBGlTMxC1C9XbTRwZrX4lTzrvyv/3oCZukD2DL+ HskS4oQQtclheap5Umya6K+M/+98ZrDYp0GDNCv3bPpDP8gEmmcuAAObMRnzs8JDhUIvrIBp4Y04G fYsZkYVGCLgtK5kUS6luWofbaHfpJFnVTBh1+z1PyBccDo+7S12Ije13zH8GN9RJbksX2yed9Qg+O AaAUiiFlKb3aTNHffBcuExxbq3kongd7MTQDttyG690o98DtzSxUS37AeGM7ZKqPkMQ3ACVsh/LiX pGfE0e8+pzikBRwo3o9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pbQ9U-003BFN-NT; Sun, 12 Mar 2023 18:10:36 +0000 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pbQ9N-003BDF-NT for linux-arm-kernel@lists.infradead.org; Sun, 12 Mar 2023 18:10:31 +0000 Received: by mail-lf1-x12e.google.com with SMTP id s20so12967254lfb.11 for ; Sun, 12 Mar 2023 11:10:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678644625; h=cc:to:subject:date:from:message-id:from:to:cc:subject:date :message-id:reply-to; bh=bdTNsWpg9ZM8ehZQeKtTu+6KMOIWutkVZQ0G5s6b6sY=; b=APYyv1vUixRQN2kiyYgXDw07Suq42jeJtEgoT2gq/wPKAODbAPh7LrpyflyeuRYQf1 c76aCXM2Y83KTdhSf7LMXhZ3iQ0qR5fj/ijkuOC+YysXUk1+3Bs3gulH3ROPA30GLVMW bxCUsxJ2WBS9OuMe+YR1WA5BMa6Z63an00BrFxwDZT/WKrsx64D06Z5Z/c2+/CzLyWMi 4wRHCipizMtdm7IZTFD//ZO+I7UhCJ9VgRZ6If101Jpl6iiyTM53BOEj86DUF0k7iM/a jxH5ffRBZjg1izma36GP6vGSiZWXeo9Oq70aPc9aIbvaPSRXdmslDtuRmvFKNwOts8dI LjCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678644625; h=cc:to:subject:date:from:message-id:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bdTNsWpg9ZM8ehZQeKtTu+6KMOIWutkVZQ0G5s6b6sY=; b=65QxWezpvZZCQx3j0mJtcIdFh3jImZhUlEqwGPSM0pYRwq3XVPzc4uBAiyzFXjBRgX wHpMDRaCqayHk5NEmphGglJbcjLgwXo5B+vwc+xS+l4hIBhfIM4XIbBOPvps2vOJjHZq SOqT1GtDFBS2AlzJEHvqzAh21ohnlpRF3uasbKm5LTHId9vfvO4srjRYFNVUuzmarkCr 4vHxV3SRRdhyv86hH2zYcR+j8cYu9V0D+7hrgmMDcLW0r+GJdhEx55+P9QPwxOmnRZxN mTx6KNA9eBajiFUoAN7BGWf5pp4mnTbQXH6maBPKJGTJDF/VZMSNk+9icQXkmDhClmtV +7Ig== X-Gm-Message-State: AO0yUKXaPln+fmTIEa1+lqCETyLolBc9HHQ9mX5isXTCfisc7HvaxMN0 8SDEKE6EC+zu26FaE3cPLMst1Q7mBto+YJvj X-Google-Smtp-Source: AK7set8kdDXVxkDtJ28JZwnYFaP6RHJPXdl9YDGbdxwRd/gqW4+nXicpW27/mERQquy9ccOq+ymTKg== X-Received: by 2002:ac2:520e:0:b0:4e8:3ef9:19bb with SMTP id a14-20020ac2520e000000b004e83ef919bbmr953751lfl.21.1678644625511; Sun, 12 Mar 2023 11:10:25 -0700 (PDT) Received: from 0000-cover-letter.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id w20-20020ac24434000000b004d19e442d53sm721046lfl.249.2023.03.12.11.10.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:10:25 -0700 (PDT) Message-Id: <1678644516.665314-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 0/3] mmc: dw_mmc: fix DW MMC cores with 32-bit bus on 64-bit Linux systems To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230312_111030_129805_B8DBECCB X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DesignWare MMC cores have a configurable data bus width of either 16, 32, or 64 bytes. It is possible, and some vendors actually do it, to ship a DW MMC core configured for 32-bit data bus within a 64-bit SoC. In this case the kernel will attempt 64-bit (readq) accesses to certain 64-bit MMIO registers, while the core will expect pairs of 32-bit accesses. It seems that currently the only register for which the kernel performs 64-bit accesses is the FIFO. The symptom is that the DW MMC core never receives a read on the second half of the register, does not register the datum as being read, and thus not advancing its internal FIFO pointer, breaking further reads. It also seems that this FIFO is only used for small (less than 16 bytes) transfers, which probably means that only some SDIO cards are affected. Changelog: v5: - rename "samsung,exynos78xx-dw-mshc" to "samsung,exynos7885-dw-mshc" - rename "samsung,exynos78xx-dw-mshc" to "samsung,exynos7885-dw-mshc" v4: - split dt-bindings and dts update into separate commits - add an explanation why it'ss necessary to change the compatible string v3: - removed "fifo-access-32bit" devicetree property - added "samsung,exynos78xx-dw-mshc" compatible string - added "samsung,exynos78xx-dw-mshc-smu" compatible string v2: - added commit messages v1: - added "fifo-access-32bit" devicetree property - added DW_MMC_QUIRK_FIFO64_32 - added new dw_mci_{pull,push}_data* variants (...-data64_32) Sergey Lisov (3): dt-bindings: exynos-dw-mshc-common: add exynos7885 variants mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO arm64: dts: exynos: fix wrong mmc compatible in exynos7885.dtsi .../bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 + arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- drivers/mmc/host/dw_mmc-exynos.c | 43 +++++- drivers/mmc/host/dw_mmc.c | 122 +++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 5 files changed, 167 insertions(+), 4 deletions(-) -- 2.38.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel