diff for duplicates of <1702684.jtWEXlagAO@jernej-laptop> diff --git a/a/1.txt b/N1/1.txt index 2070f87..7a43e45 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,93 +1,87 @@ Dne sreda, 12. september 2018 ob 14:20:08 CEST je Chen-Yu Tsai napisal(a): -> On Wed, Sep 5, 2018 at 1:46 AM Jernej =C5=A0krabec <jernej.skrabec@siol.n= -et>=20 +> On Wed, Sep 5, 2018 at 1:46 AM Jernej ?krabec <jernej.skrabec@siol.net> wrote: -> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(= -a): -> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.ne= -t> -> >=20 +> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a): +> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.net> +> > > > wrote: > > > > Support for mixer0, mixer1, writeback and rotation units is added. -> > > >=20 +> > > > > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > > --- -> > > >=20 +> > > > > > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65 > > > > ++++++++++++++++++++++++++++ > > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 + > > > > 2 files changed, 66 insertions(+) -> > > >=20 +> > > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index > > > > bae5ee67a797..4535c1c27d27 > > > > 100644 > > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c -> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1= -", +> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", > > > > "bus-de",> -> > > >=20 +> > > > > > > > 0x04, BIT(1), 0); -> > > > =20 +> > > > > > > > static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de", -> > > > =20 +> > > > > > > > 0x04, BIT(2), 0); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de", > > > > + 0x04, BIT(3), 0); -> > > >=20 -> > > > static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div= -", -> > > > =20 +> > > > +> > > > static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div", +> > > > > > > > 0x00, BIT(0), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, "mixer1", > > > > "mixer1-div",> -> > > >=20 +> > > > > > > > 0x00, BIT(1), CLK_SET_RATE_PARENT); -> > > > =20 +> > > > > > > > static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", -> > > > =20 +> > > > > > > > 0x00, BIT(2), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div", > > > > + 0x00, BIT(3), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", > > > > "de", > > > > 0x0c, 4, 4,> -> > > >=20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > > =20 +> > > > > > > > static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4, > > > > + CLK_SET_RATE_PARENT); -> > > >=20 -> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0= -c, +> > > > +> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, > > > > 0, > > > > 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, > > > > "mixer1-div", > > > > "pll-de", 0x0c, 4, 4,> -> > > >=20 +> > > > > > > > static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 -> > > > +static struct ccu_common *sun50i_h6_de3_clks[] =3D { +> > > > +> > > > +static struct ccu_common *sun50i_h6_de3_clks[] = { > > > > + &mixer0_clk.common, > > > > + &mixer1_clk.common, > > > > + &wb_clk.common, @@ -105,149 +99,142 @@ c, > > > > + &rot_div_clk.common, > > > > +}; > > > > + -> > > >=20 -> > > > static struct ccu_common *sun8i_a83t_de2_clks[] =3D { -> > > > =20 +> > > > +> > > > static struct ccu_common *sun8i_a83t_de2_clks[] = { +> > > > > > > > &mixer0_clk.common, > > > > &mixer1_clk.common, -> > > >=20 -> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = -=3D { -> > > >=20 +> > > > +> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = { +> > > > > > > > &wb_div_clk.common, -> > > > =20 +> > > > > > > > }; -> > > >=20 -> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks =3D { -> > > > + .hws =3D { -> > > > + [CLK_MIXER0] =3D &mixer0_clk.common.hw, -> > > > + [CLK_MIXER1] =3D &mixer1_clk.common.hw, -> > > > + [CLK_WB] =3D &wb_clk.common.hw, -> > > > + [CLK_ROT] =3D &rot_clk.common.hw, +> > > > +> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = { +> > > > + .hws = { +> > > > + [CLK_MIXER0] = &mixer0_clk.common.hw, +> > > > + [CLK_MIXER1] = &mixer1_clk.common.hw, +> > > > + [CLK_WB] = &wb_clk.common.hw, +> > > > + [CLK_ROT] = &rot_clk.common.hw, > > > > + -> > > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_clk.common.= -hw, -> > > > + [CLK_BUS_MIXER1] =3D &bus_mixer1_clk.common.= -hw, -> > > > + [CLK_BUS_WB] =3D &bus_wb_clk.common.hw, -> > > > + [CLK_BUS_ROT] =3D &bus_rot_clk.common.hw, +> > > > + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, +> > > > + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, +> > > > + [CLK_BUS_WB] = &bus_wb_clk.common.hw, +> > > > + [CLK_BUS_ROT] = &bus_rot_clk.common.hw, > > > > + -> > > > + [CLK_MIXER0_DIV] =3D &mixer0_div_clk.common.= -hw, -> > > > + [CLK_MIXER1_DIV] =3D &mixer1_div_clk.common.= -hw, -> > > > + [CLK_WB_DIV] =3D &wb_div_clk.common.hw, -> > > > + [CLK_ROT_DIV] =3D &rot_div_clk.common.hw, +> > > > + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, +> > > > + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, +> > > > + [CLK_WB_DIV] = &wb_div_clk.common.hw, +> > > > + [CLK_ROT_DIV] = &rot_div_clk.common.hw, > > > > + }, -> > > > + .num =3D 12, -> > >=20 +> > > > + .num = 12, +> > > > > > It's best not to openly code these. It is error prone, like having > > > an index beyond .num, which then never gets registered. -> > >=20 +> > > > > > Instead, please update CLK_NUMBERS and use that instead. > > > sunxi_ccu_probe() > > > can handle holes in .hws. -> >=20 -> > I'm not sure this will work. All newly introduced indices are at the en= -d, +> > +> > I'm not sure this will work. All newly introduced indices are at the end, > > so other arrays will still have same length (hole at the end). You will > > just claim that arrays are larger than they really are, which means bad > > things. -> >=20 -> > But I take any other suggestion. I really can't think of better solutio= -n. ->=20 +> > +> > But I take any other suggestion. I really can't think of better solution. +> > Then maybe have macros for both cases instead? > CLK_NUMBER_WITH_ROT / CLK_NUMBER_WITHOUT_ROT? -That sounds reasonable. Do you want separate patch which renames original=20 +That sounds reasonable. Do you want separate patch which renames original macro CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT? Best regards, Jernej ->=20 +> > ChenYu ->=20 +> > > Best regards, > > Jernej -> >=20 +> > > > > On the other hand, it can't handle holes in the ccu_reset_map. Hope we > > > never have to deal with such an instance. -> > >=20 +> > > > > > ChenYu -> > >=20 +> > > > > > > +}; > > > > + -> > > >=20 -> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks =3D { -> > > > =20 -> > > > .hws =3D { -> > > > =20 -> > > > [CLK_MIXER0] =3D &mixer0_clk.common.hw, -> > > >=20 +> > > > +> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { +> > > > +> > > > .hws = { +> > > > +> > > > [CLK_MIXER0] = &mixer0_clk.common.hw, +> > > > > > > > @@ -156,6 +200,13 @@ static struct ccu_reset_map -> > > > sun50i_a64_de2_resets[] =3D +> > > > sun50i_a64_de2_resets[] = > > > > {> -> > > >=20 -> > > > [RST_WB] =3D { 0x08, BIT(2) }, -> > > > =20 +> > > > +> > > > [RST_WB] = { 0x08, BIT(2) }, +> > > > > > > > }; -> > > >=20 -> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] =3D { -> > > > + [RST_MIXER0] =3D { 0x08, BIT(0) }, -> > > > + [RST_MIXER1] =3D { 0x08, BIT(1) }, -> > > > + [RST_WB] =3D { 0x08, BIT(2) }, -> > > > + [RST_ROT] =3D { 0x08, BIT(3) }, +> > > > +> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] = { +> > > > + [RST_MIXER0] = { 0x08, BIT(0) }, +> > > > + [RST_MIXER1] = { 0x08, BIT(1) }, +> > > > + [RST_WB] = { 0x08, BIT(2) }, +> > > > + [RST_ROT] = { 0x08, BIT(3) }, > > > > +}; > > > > + -> > > >=20 -> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc =3D { -> > > > =20 -> > > > .ccu_clks =3D sun8i_a83t_de2_clks, -> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks), -> > > >=20 +> > > > +> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { +> > > > +> > > > .ccu_clks = sun8i_a83t_de2_clks, +> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), +> > > > > > > > @@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc -> > > > sun50i_a64_de2_clk_desc =3D {> -> > > >=20 -> > > > .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets), -> > > > =20 +> > > > sun50i_a64_de2_clk_desc = {> +> > > > +> > > > .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), +> > > > > > > > }; -> > > >=20 -> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc =3D { -> > > > + .ccu_clks =3D sun50i_h6_de3_clks, -> > > > + .num_ccu_clks =3D ARRAY_SIZE(sun50i_h6_de3_clks), +> > > > +> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = { +> > > > + .ccu_clks = sun50i_h6_de3_clks, +> > > > + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks), > > > > + -> > > > + .hw_clks =3D &sun50i_h6_de3_hw_clks, +> > > > + .hw_clks = &sun50i_h6_de3_hw_clks, > > > > + -> > > > + .resets =3D sun50i_h6_de3_resets, -> > > > + .num_resets =3D ARRAY_SIZE(sun50i_h6_de3_resets), +> > > > + .resets = sun50i_h6_de3_resets, +> > > > + .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets), > > > > +}; > > > > + -> > > >=20 -> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc =3D { -> > > > =20 -> > > > .ccu_clks =3D sun8i_v3s_de2_clks, -> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_v3s_de2_clks), -> > > >=20 +> > > > +> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { +> > > > +> > > > .ccu_clks = sun8i_v3s_de2_clks, +> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), +> > > > > > > > @@ -296,6 +357,10 @@ static const struct of_device_id > > > > sunxi_de2_clk_ids[] -> > > > =3D {> -> > > >=20 -> > > > .compatible =3D "allwinner,sun50i-h5-de2-clk", -> > > > .data =3D &sun50i_a64_de2_clk_desc, -> > > > =20 +> > > > = {> +> > > > +> > > > .compatible = "allwinner,sun50i-h5-de2-clk", +> > > > .data = &sun50i_a64_de2_clk_desc, +> > > > > > > > }, -> > > >=20 +> > > > > > > > + { -> > > > + .compatible =3D "allwinner,sun50i-h6-de3-clk", -> > > > + .data =3D &sun50i_h6_de3_clk_desc, +> > > > + .compatible = "allwinner,sun50i-h6-de3-clk", +> > > > + .data = &sun50i_h6_de3_clk_desc, > > > > + }, -> > > >=20 +> > > > > > > > { } -> > > > =20 +> > > > > > > > }; -> > > >=20 +> > > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h index > > > > 530c006e0ae9..27bd88539f42 @@ -255,14 +242,14 @@ Jernej > > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > @@ -22,6 +22,7 @@ -> > > >=20 +> > > > > > > > #define CLK_MIXER0_DIV 3 > > > > #define CLK_MIXER1_DIV 4 > > > > #define CLK_WB_DIV 5 -> > > >=20 +> > > > > > > > +#define CLK_ROT_DIV 11 -> > > >=20 +> > > > > > > > #define CLK_NUMBER (CLK_WB + 1) -> > > >=20 +> > > > > > > > -- > > > > 2.18.0 diff --git a/a/content_digest b/N1/content_digest index 0af2ffe..29d2328 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,117 +1,96 @@ "ref\020180902072643.4917-1-jernej.skrabec@siol.net\0" "ref\01677668.BePkXd9qNa@jernej-laptop\0" "ref\0CAGb2v66kojjjM4f_tO9NwzkCzD3LMM2eiq+PJ6Bk=1Rra=UnYg@mail.gmail.com\0" - "From\0Jernej \305\240krabec <jernej.skrabec@siol.net>\0" - "Subject\0Re: [PATCH 08/27] clk: sunxi-ng: Add support for H6 DE3 clocks\0" + "From\0jernej.skrabec@siol.net (Jernej \305\240krabec)\0" + "Subject\0[PATCH 08/27] clk: sunxi-ng: Add support for H6 DE3 clocks\0" "Date\0Wed, 12 Sep 2018 16:55:07 +0200\0" - "To\0Chen-Yu Tsai <wens@csie.org>\0" - "Cc\0Rob Herring <robh+dt@kernel.org>" - Maxime Ripard <maxime.ripard@bootlin.com> - Mark Rutland <mark.rutland@arm.com> - Mike Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@kernel.org> - David Airlie <airlied@linux.ie> - Archit Taneja <architt@codeaurora.org> - Andrzej Hajda <a.hajda@samsung.com> - devicetree <devicetree@vger.kernel.org> - linux-arm-kernel <linux-arm-kernel@lists.infradead.org> - linux-kernel <linux-kernel@vger.kernel.org> - linux-clk <linux-clk@vger.kernel.org> - dri-devel <dri-devel@lists.freedesktop.org> - linux-sunxi <linux-sunxi@googlegroups.com> - " Icenowy Zheng <icenowy@aosc.io>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Dne sreda, 12. september 2018 ob 14:20:08 CEST je Chen-Yu Tsai napisal(a):\n" - "> On Wed, Sep 5, 2018 at 1:46 AM Jernej =C5=A0krabec <jernej.skrabec@siol.n=\n" - "et>=20\n" + "> On Wed, Sep 5, 2018 at 1:46 AM Jernej ?krabec <jernej.skrabec@siol.net> \n" "wrote:\n" - "> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(=\n" - "a):\n" - "> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.ne=\n" - "t>\n" - "> >=20\n" + "> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a):\n" + "> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.net>\n" + "> > \n" "> > wrote:\n" "> > > > Support for mixer0, mixer1, writeback and rotation units is added.\n" - "> > > >=20\n" + "> > > > \n" "> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n" "> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n" "> > > > ---\n" - "> > > >=20\n" + "> > > > \n" "> > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65\n" "> > > > ++++++++++++++++++++++++++++\n" "> > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 +\n" "> > > > 2 files changed, 66 insertions(+)\n" - "> > > >=20\n" + "> > > > \n" "> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" "> > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index\n" "> > > > bae5ee67a797..4535c1c27d27\n" "> > > > 100644\n" "> > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" "> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" - "> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, \"bus-mixer1=\n" - "\",\n" + "> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, \"bus-mixer1\",\n" "> > > > \"bus-de\",>\n" - "> > > >=20\n" + "> > > > \n" "> > > > 0x04, BIT(1), 0);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_GATE(bus_wb_clk, \"bus-wb\", \"bus-de\",\n" - "> > > > =20\n" + "> > > > \n" "> > > > 0x04, BIT(2), 0);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_GATE(bus_rot_clk, \"bus-rot\", \"bus-de\",\n" "> > > > + 0x04, BIT(3), 0);\n" - "> > > >=20\n" - "> > > > static SUNXI_CCU_GATE(mixer0_clk, \"mixer0\", \"mixer0-div=\n" - "\",\n" - "> > > > =20\n" + "> > > > \n" + "> > > > static SUNXI_CCU_GATE(mixer0_clk, \"mixer0\", \"mixer0-div\",\n" + "> > > > \n" "> > > > 0x00, BIT(0), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, \"mixer1\",\n" "> > > > \"mixer1-div\",>\n" - "> > > >=20\n" + "> > > > \n" "> > > > 0x00, BIT(1), CLK_SET_RATE_PARENT);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_GATE(wb_clk, \"wb\", \"wb-div\",\n" - "> > > > =20\n" + "> > > > \n" "> > > > 0x00, BIT(2), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_GATE(rot_clk, \"rot\", \"rot-div\",\n" "> > > > + 0x00, BIT(3), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(mixer0_div_clk, \"mixer0-div\", \"de\", 0x0c, 0, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, \"mixer1-div\",\n" "> > > > \"de\",\n" "> > > > 0x0c, 4, 4,>\n" - "> > > >=20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(wb_div_clk, \"wb-div\", \"de\", 0x0c, 8, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_M(rot_div_clk, \"rot-div\", \"de\", 0x0c, 0x0c, 4,\n" "> > > > + CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" - "> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, \"mixer0-div\", \"pll-de\", 0x0=\n" - "c,\n" + "> > > > \n" + "> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, \"mixer0-div\", \"pll-de\", 0x0c,\n" "> > > > 0,\n" "> > > > 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk,\n" "> > > > \"mixer1-div\",\n" "> > > > \"pll-de\", 0x0c, 4, 4,>\n" - "> > > >=20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(wb_div_a83_clk, \"wb-div\", \"pll-de\", 0x0c, 8, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" - "> > > > +static struct ccu_common *sun50i_h6_de3_clks[] =3D {\n" + "> > > > \n" + "> > > > +static struct ccu_common *sun50i_h6_de3_clks[] = {\n" "> > > > + &mixer0_clk.common,\n" "> > > > + &mixer1_clk.common,\n" "> > > > + &wb_clk.common,\n" @@ -129,149 +108,142 @@ "> > > > + &rot_div_clk.common,\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static struct ccu_common *sun8i_a83t_de2_clks[] =3D {\n" - "> > > > =20\n" + "> > > > \n" + "> > > > static struct ccu_common *sun8i_a83t_de2_clks[] = {\n" + "> > > > \n" "> > > > &mixer0_clk.common,\n" "> > > > &mixer1_clk.common,\n" - "> > > >=20\n" - "> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] =\n" - "=3D {\n" - "> > > >=20\n" + "> > > > \n" + "> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {\n" + "> > > > \n" "> > > > &wb_div_clk.common,\n" - "> > > > =20\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks =3D {\n" - "> > > > + .hws =3D {\n" - "> > > > + [CLK_MIXER0] =3D &mixer0_clk.common.hw,\n" - "> > > > + [CLK_MIXER1] =3D &mixer1_clk.common.hw,\n" - "> > > > + [CLK_WB] =3D &wb_clk.common.hw,\n" - "> > > > + [CLK_ROT] =3D &rot_clk.common.hw,\n" + "> > > > \n" + "> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {\n" + "> > > > + .hws = {\n" + "> > > > + [CLK_MIXER0] = &mixer0_clk.common.hw,\n" + "> > > > + [CLK_MIXER1] = &mixer1_clk.common.hw,\n" + "> > > > + [CLK_WB] = &wb_clk.common.hw,\n" + "> > > > + [CLK_ROT] = &rot_clk.common.hw,\n" "> > > > +\n" - "> > > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_BUS_MIXER1] =3D &bus_mixer1_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_BUS_WB] =3D &bus_wb_clk.common.hw,\n" - "> > > > + [CLK_BUS_ROT] =3D &bus_rot_clk.common.hw,\n" + "> > > > + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,\n" + "> > > > + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,\n" + "> > > > + [CLK_BUS_WB] = &bus_wb_clk.common.hw,\n" + "> > > > + [CLK_BUS_ROT] = &bus_rot_clk.common.hw,\n" "> > > > +\n" - "> > > > + [CLK_MIXER0_DIV] =3D &mixer0_div_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_MIXER1_DIV] =3D &mixer1_div_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_WB_DIV] =3D &wb_div_clk.common.hw,\n" - "> > > > + [CLK_ROT_DIV] =3D &rot_div_clk.common.hw,\n" + "> > > > + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,\n" + "> > > > + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,\n" + "> > > > + [CLK_WB_DIV] = &wb_div_clk.common.hw,\n" + "> > > > + [CLK_ROT_DIV] = &rot_div_clk.common.hw,\n" "> > > > + },\n" - "> > > > + .num =3D 12,\n" - "> > >=20\n" + "> > > > + .num = 12,\n" + "> > > \n" "> > > It's best not to openly code these. It is error prone, like having\n" "> > > an index beyond .num, which then never gets registered.\n" - "> > >=20\n" + "> > > \n" "> > > Instead, please update CLK_NUMBERS and use that instead.\n" "> > > sunxi_ccu_probe()\n" "> > > can handle holes in .hws.\n" - "> >=20\n" - "> > I'm not sure this will work. All newly introduced indices are at the en=\n" - "d,\n" + "> > \n" + "> > I'm not sure this will work. All newly introduced indices are at the end,\n" "> > so other arrays will still have same length (hole at the end). You will\n" "> > just claim that arrays are larger than they really are, which means bad\n" "> > things.\n" - "> >=20\n" - "> > But I take any other suggestion. I really can't think of better solutio=\n" - "n.\n" - ">=20\n" + "> > \n" + "> > But I take any other suggestion. I really can't think of better solution.\n" + "> \n" "> Then maybe have macros for both cases instead?\n" "> CLK_NUMBER_WITH_ROT / CLK_NUMBER_WITHOUT_ROT?\n" "\n" - "That sounds reasonable. Do you want separate patch which renames original=20\n" + "That sounds reasonable. Do you want separate patch which renames original \n" "macro CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT?\n" "\n" "Best regards,\n" "Jernej\n" "\n" - ">=20\n" + "> \n" "> ChenYu\n" - ">=20\n" + "> \n" "> > Best regards,\n" "> > Jernej\n" - "> >=20\n" + "> > \n" "> > > On the other hand, it can't handle holes in the ccu_reset_map. Hope we\n" "> > > never have to deal with such an instance.\n" - "> > >=20\n" + "> > > \n" "> > > ChenYu\n" - "> > >=20\n" + "> > > \n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks =3D {\n" - "> > > > =20\n" - "> > > > .hws =3D {\n" - "> > > > =20\n" - "> > > > [CLK_MIXER0] =3D &mixer0_clk.common.hw,\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {\n" + "> > > > \n" + "> > > > .hws = {\n" + "> > > > \n" + "> > > > [CLK_MIXER0] = &mixer0_clk.common.hw,\n" + "> > > > \n" "> > > > @@ -156,6 +200,13 @@ static struct ccu_reset_map\n" - "> > > > sun50i_a64_de2_resets[] =3D\n" + "> > > > sun50i_a64_de2_resets[] =\n" "> > > > {>\n" - "> > > >=20\n" - "> > > > [RST_WB] =3D { 0x08, BIT(2) },\n" - "> > > > =20\n" + "> > > > \n" + "> > > > [RST_WB] = { 0x08, BIT(2) },\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] =3D {\n" - "> > > > + [RST_MIXER0] =3D { 0x08, BIT(0) },\n" - "> > > > + [RST_MIXER1] =3D { 0x08, BIT(1) },\n" - "> > > > + [RST_WB] =3D { 0x08, BIT(2) },\n" - "> > > > + [RST_ROT] =3D { 0x08, BIT(3) },\n" + "> > > > \n" + "> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] = {\n" + "> > > > + [RST_MIXER0] = { 0x08, BIT(0) },\n" + "> > > > + [RST_MIXER1] = { 0x08, BIT(1) },\n" + "> > > > + [RST_WB] = { 0x08, BIT(2) },\n" + "> > > > + [RST_ROT] = { 0x08, BIT(3) },\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc =3D {\n" - "> > > > =20\n" - "> > > > .ccu_clks =3D sun8i_a83t_de2_clks,\n" - "> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks),\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {\n" + "> > > > \n" + "> > > > .ccu_clks = sun8i_a83t_de2_clks,\n" + "> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),\n" + "> > > > \n" "> > > > @@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc\n" - "> > > > sun50i_a64_de2_clk_desc =3D {>\n" - "> > > >=20\n" - "> > > > .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets),\n" - "> > > > =20\n" + "> > > > sun50i_a64_de2_clk_desc = {>\n" + "> > > > \n" + "> > > > .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc =3D {\n" - "> > > > + .ccu_clks =3D sun50i_h6_de3_clks,\n" - "> > > > + .num_ccu_clks =3D ARRAY_SIZE(sun50i_h6_de3_clks),\n" + "> > > > \n" + "> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {\n" + "> > > > + .ccu_clks = sun50i_h6_de3_clks,\n" + "> > > > + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),\n" "> > > > +\n" - "> > > > + .hw_clks =3D &sun50i_h6_de3_hw_clks,\n" + "> > > > + .hw_clks = &sun50i_h6_de3_hw_clks,\n" "> > > > +\n" - "> > > > + .resets =3D sun50i_h6_de3_resets,\n" - "> > > > + .num_resets =3D ARRAY_SIZE(sun50i_h6_de3_resets),\n" + "> > > > + .resets = sun50i_h6_de3_resets,\n" + "> > > > + .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc =3D {\n" - "> > > > =20\n" - "> > > > .ccu_clks =3D sun8i_v3s_de2_clks,\n" - "> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_v3s_de2_clks),\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {\n" + "> > > > \n" + "> > > > .ccu_clks = sun8i_v3s_de2_clks,\n" + "> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),\n" + "> > > > \n" "> > > > @@ -296,6 +357,10 @@ static const struct of_device_id\n" "> > > > sunxi_de2_clk_ids[]\n" - "> > > > =3D {>\n" - "> > > >=20\n" - "> > > > .compatible =3D \"allwinner,sun50i-h5-de2-clk\",\n" - "> > > > .data =3D &sun50i_a64_de2_clk_desc,\n" - "> > > > =20\n" + "> > > > = {>\n" + "> > > > \n" + "> > > > .compatible = \"allwinner,sun50i-h5-de2-clk\",\n" + "> > > > .data = &sun50i_a64_de2_clk_desc,\n" + "> > > > \n" "> > > > },\n" - "> > > >=20\n" + "> > > > \n" "> > > > + {\n" - "> > > > + .compatible =3D \"allwinner,sun50i-h6-de3-clk\",\n" - "> > > > + .data =3D &sun50i_h6_de3_clk_desc,\n" + "> > > > + .compatible = \"allwinner,sun50i-h6-de3-clk\",\n" + "> > > > + .data = &sun50i_h6_de3_clk_desc,\n" "> > > > + },\n" - "> > > >=20\n" + "> > > > \n" "> > > > { }\n" - "> > > > =20\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" + "> > > > \n" "> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h index\n" "> > > > 530c006e0ae9..27bd88539f42\n" @@ -279,16 +251,16 @@ "> > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > @@ -22,6 +22,7 @@\n" - "> > > >=20\n" + "> > > > \n" "> > > > #define CLK_MIXER0_DIV 3\n" "> > > > #define CLK_MIXER1_DIV 4\n" "> > > > #define CLK_WB_DIV 5\n" - "> > > >=20\n" + "> > > > \n" "> > > > +#define CLK_ROT_DIV 11\n" - "> > > >=20\n" + "> > > > \n" "> > > > #define CLK_NUMBER (CLK_WB + 1)\n" - "> > > >=20\n" + "> > > > \n" "> > > > --\n" > > > > 2.18.0 -66dcf48964934fd7e865d8cdad6a01d8b0ecaa1a81ea2efc61ecbd02da2d8a40 +675c03b83f2aa524de2c1e5b05e9aaa457e769e5d79ad11da15dac23c9f51981
diff --git a/a/1.txt b/N2/1.txt index 2070f87..74b5036 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,93 +1,87 @@ Dne sreda, 12. september 2018 ob 14:20:08 CEST je Chen-Yu Tsai napisal(a): -> On Wed, Sep 5, 2018 at 1:46 AM Jernej =C5=A0krabec <jernej.skrabec@siol.n= -et>=20 +> On Wed, Sep 5, 2018 at 1:46 AM Jernej Škrabec <jernej.skrabec@siol.net> wrote: -> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(= -a): -> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.ne= -t> -> >=20 +> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a): +> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec-ix9DCk4F938@public.gmane.orgt> +> > > > wrote: > > > > Support for mixer0, mixer1, writeback and rotation units is added. -> > > >=20 -> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> -> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +> > > > +> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org> +> > > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> > > > > --- -> > > >=20 +> > > > > > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65 > > > > ++++++++++++++++++++++++++++ > > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 + > > > > 2 files changed, 66 insertions(+) -> > > >=20 +> > > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index > > > > bae5ee67a797..4535c1c27d27 > > > > 100644 > > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c -> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1= -", +> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", > > > > "bus-de",> -> > > >=20 +> > > > > > > > 0x04, BIT(1), 0); -> > > > =20 +> > > > > > > > static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de", -> > > > =20 +> > > > > > > > 0x04, BIT(2), 0); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de", > > > > + 0x04, BIT(3), 0); -> > > >=20 -> > > > static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div= -", -> > > > =20 +> > > > +> > > > static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div", +> > > > > > > > 0x00, BIT(0), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, "mixer1", > > > > "mixer1-div",> -> > > >=20 +> > > > > > > > 0x00, BIT(1), CLK_SET_RATE_PARENT); -> > > > =20 +> > > > > > > > static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", -> > > > =20 +> > > > > > > > 0x00, BIT(2), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div", > > > > + 0x00, BIT(3), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", > > > > "de", > > > > 0x0c, 4, 4,> -> > > >=20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > > =20 +> > > > > > > > static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4, > > > > + CLK_SET_RATE_PARENT); -> > > >=20 -> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0= -c, +> > > > +> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, > > > > 0, > > > > 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, > > > > "mixer1-div", > > > > "pll-de", 0x0c, 4, 4,> -> > > >=20 +> > > > > > > > static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 -> > > > +static struct ccu_common *sun50i_h6_de3_clks[] =3D { +> > > > +> > > > +static struct ccu_common *sun50i_h6_de3_clks[] = { > > > > + &mixer0_clk.common, > > > > + &mixer1_clk.common, > > > > + &wb_clk.common, @@ -105,149 +99,142 @@ c, > > > > + &rot_div_clk.common, > > > > +}; > > > > + -> > > >=20 -> > > > static struct ccu_common *sun8i_a83t_de2_clks[] =3D { -> > > > =20 +> > > > +> > > > static struct ccu_common *sun8i_a83t_de2_clks[] = { +> > > > > > > > &mixer0_clk.common, > > > > &mixer1_clk.common, -> > > >=20 -> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = -=3D { -> > > >=20 +> > > > +> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = { +> > > > > > > > &wb_div_clk.common, -> > > > =20 +> > > > > > > > }; -> > > >=20 -> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks =3D { -> > > > + .hws =3D { -> > > > + [CLK_MIXER0] =3D &mixer0_clk.common.hw, -> > > > + [CLK_MIXER1] =3D &mixer1_clk.common.hw, -> > > > + [CLK_WB] =3D &wb_clk.common.hw, -> > > > + [CLK_ROT] =3D &rot_clk.common.hw, +> > > > +> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = { +> > > > + .hws = { +> > > > + [CLK_MIXER0] = &mixer0_clk.common.hw, +> > > > + [CLK_MIXER1] = &mixer1_clk.common.hw, +> > > > + [CLK_WB] = &wb_clk.common.hw, +> > > > + [CLK_ROT] = &rot_clk.common.hw, > > > > + -> > > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_clk.common.= -hw, -> > > > + [CLK_BUS_MIXER1] =3D &bus_mixer1_clk.common.= -hw, -> > > > + [CLK_BUS_WB] =3D &bus_wb_clk.common.hw, -> > > > + [CLK_BUS_ROT] =3D &bus_rot_clk.common.hw, +> > > > + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, +> > > > + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, +> > > > + [CLK_BUS_WB] = &bus_wb_clk.common.hw, +> > > > + [CLK_BUS_ROT] = &bus_rot_clk.common.hw, > > > > + -> > > > + [CLK_MIXER0_DIV] =3D &mixer0_div_clk.common.= -hw, -> > > > + [CLK_MIXER1_DIV] =3D &mixer1_div_clk.common.= -hw, -> > > > + [CLK_WB_DIV] =3D &wb_div_clk.common.hw, -> > > > + [CLK_ROT_DIV] =3D &rot_div_clk.common.hw, +> > > > + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, +> > > > + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, +> > > > + [CLK_WB_DIV] = &wb_div_clk.common.hw, +> > > > + [CLK_ROT_DIV] = &rot_div_clk.common.hw, > > > > + }, -> > > > + .num =3D 12, -> > >=20 +> > > > + .num = 12, +> > > > > > It's best not to openly code these. It is error prone, like having > > > an index beyond .num, which then never gets registered. -> > >=20 +> > > > > > Instead, please update CLK_NUMBERS and use that instead. > > > sunxi_ccu_probe() > > > can handle holes in .hws. -> >=20 -> > I'm not sure this will work. All newly introduced indices are at the en= -d, +> > +> > I'm not sure this will work. All newly introduced indices are at the end, > > so other arrays will still have same length (hole at the end). You will > > just claim that arrays are larger than they really are, which means bad > > things. -> >=20 -> > But I take any other suggestion. I really can't think of better solutio= -n. ->=20 +> > +> > But I take any other suggestion. I really can't think of better solution. +> > Then maybe have macros for both cases instead? > CLK_NUMBER_WITH_ROT / CLK_NUMBER_WITHOUT_ROT? -That sounds reasonable. Do you want separate patch which renames original=20 +That sounds reasonable. Do you want separate patch which renames original macro CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT? Best regards, Jernej ->=20 +> > ChenYu ->=20 +> > > Best regards, > > Jernej -> >=20 +> > > > > On the other hand, it can't handle holes in the ccu_reset_map. Hope we > > > never have to deal with such an instance. -> > >=20 +> > > > > > ChenYu -> > >=20 +> > > > > > > +}; > > > > + -> > > >=20 -> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks =3D { -> > > > =20 -> > > > .hws =3D { -> > > > =20 -> > > > [CLK_MIXER0] =3D &mixer0_clk.common.hw, -> > > >=20 +> > > > +> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { +> > > > +> > > > .hws = { +> > > > +> > > > [CLK_MIXER0] = &mixer0_clk.common.hw, +> > > > > > > > @@ -156,6 +200,13 @@ static struct ccu_reset_map -> > > > sun50i_a64_de2_resets[] =3D +> > > > sun50i_a64_de2_resets[] = > > > > {> -> > > >=20 -> > > > [RST_WB] =3D { 0x08, BIT(2) }, -> > > > =20 +> > > > +> > > > [RST_WB] = { 0x08, BIT(2) }, +> > > > > > > > }; -> > > >=20 -> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] =3D { -> > > > + [RST_MIXER0] =3D { 0x08, BIT(0) }, -> > > > + [RST_MIXER1] =3D { 0x08, BIT(1) }, -> > > > + [RST_WB] =3D { 0x08, BIT(2) }, -> > > > + [RST_ROT] =3D { 0x08, BIT(3) }, +> > > > +> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] = { +> > > > + [RST_MIXER0] = { 0x08, BIT(0) }, +> > > > + [RST_MIXER1] = { 0x08, BIT(1) }, +> > > > + [RST_WB] = { 0x08, BIT(2) }, +> > > > + [RST_ROT] = { 0x08, BIT(3) }, > > > > +}; > > > > + -> > > >=20 -> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc =3D { -> > > > =20 -> > > > .ccu_clks =3D sun8i_a83t_de2_clks, -> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks), -> > > >=20 +> > > > +> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { +> > > > +> > > > .ccu_clks = sun8i_a83t_de2_clks, +> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), +> > > > > > > > @@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc -> > > > sun50i_a64_de2_clk_desc =3D {> -> > > >=20 -> > > > .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets), -> > > > =20 +> > > > sun50i_a64_de2_clk_desc = {> +> > > > +> > > > .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), +> > > > > > > > }; -> > > >=20 -> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc =3D { -> > > > + .ccu_clks =3D sun50i_h6_de3_clks, -> > > > + .num_ccu_clks =3D ARRAY_SIZE(sun50i_h6_de3_clks), +> > > > +> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = { +> > > > + .ccu_clks = sun50i_h6_de3_clks, +> > > > + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks), > > > > + -> > > > + .hw_clks =3D &sun50i_h6_de3_hw_clks, +> > > > + .hw_clks = &sun50i_h6_de3_hw_clks, > > > > + -> > > > + .resets =3D sun50i_h6_de3_resets, -> > > > + .num_resets =3D ARRAY_SIZE(sun50i_h6_de3_resets), +> > > > + .resets = sun50i_h6_de3_resets, +> > > > + .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets), > > > > +}; > > > > + -> > > >=20 -> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc =3D { -> > > > =20 -> > > > .ccu_clks =3D sun8i_v3s_de2_clks, -> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_v3s_de2_clks), -> > > >=20 +> > > > +> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { +> > > > +> > > > .ccu_clks = sun8i_v3s_de2_clks, +> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), +> > > > > > > > @@ -296,6 +357,10 @@ static const struct of_device_id > > > > sunxi_de2_clk_ids[] -> > > > =3D {> -> > > >=20 -> > > > .compatible =3D "allwinner,sun50i-h5-de2-clk", -> > > > .data =3D &sun50i_a64_de2_clk_desc, -> > > > =20 +> > > > = {> +> > > > +> > > > .compatible = "allwinner,sun50i-h5-de2-clk", +> > > > .data = &sun50i_a64_de2_clk_desc, +> > > > > > > > }, -> > > >=20 +> > > > > > > > + { -> > > > + .compatible =3D "allwinner,sun50i-h6-de3-clk", -> > > > + .data =3D &sun50i_h6_de3_clk_desc, +> > > > + .compatible = "allwinner,sun50i-h6-de3-clk", +> > > > + .data = &sun50i_h6_de3_clk_desc, > > > > + }, -> > > >=20 +> > > > > > > > { } -> > > > =20 +> > > > > > > > }; -> > > >=20 +> > > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h index > > > > 530c006e0ae9..27bd88539f42 @@ -255,14 +242,22 @@ Jernej > > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > @@ -22,6 +22,7 @@ -> > > >=20 +> > > > > > > > #define CLK_MIXER0_DIV 3 > > > > #define CLK_MIXER1_DIV 4 > > > > #define CLK_WB_DIV 5 -> > > >=20 +> > > > > > > > +#define CLK_ROT_DIV 11 -> > > >=20 +> > > > > > > > #define CLK_NUMBER (CLK_WB + 1) -> > > >=20 +> > > > > > > > -- > > > > 2.18.0 + + + + +-- +You received this message because you are subscribed to the Google Groups "linux-sunxi" group. +To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org +For more options, visit https://groups.google.com/d/optout. diff --git a/a/content_digest b/N2/content_digest index 0af2ffe..422fcf6 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,117 +1,112 @@ "ref\020180902072643.4917-1-jernej.skrabec@siol.net\0" "ref\01677668.BePkXd9qNa@jernej-laptop\0" "ref\0CAGb2v66kojjjM4f_tO9NwzkCzD3LMM2eiq+PJ6Bk=1Rra=UnYg@mail.gmail.com\0" - "From\0Jernej \305\240krabec <jernej.skrabec@siol.net>\0" + "ref\0CAGb2v66kojjjM4f_tO9NwzkCzD3LMM2eiq+PJ6Bk=1Rra=UnYg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Jernej \305\240krabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>\0" "Subject\0Re: [PATCH 08/27] clk: sunxi-ng: Add support for H6 DE3 clocks\0" "Date\0Wed, 12 Sep 2018 16:55:07 +0200\0" - "To\0Chen-Yu Tsai <wens@csie.org>\0" - "Cc\0Rob Herring <robh+dt@kernel.org>" - Maxime Ripard <maxime.ripard@bootlin.com> - Mark Rutland <mark.rutland@arm.com> - Mike Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@kernel.org> - David Airlie <airlied@linux.ie> - Archit Taneja <architt@codeaurora.org> - Andrzej Hajda <a.hajda@samsung.com> - devicetree <devicetree@vger.kernel.org> - linux-arm-kernel <linux-arm-kernel@lists.infradead.org> - linux-kernel <linux-kernel@vger.kernel.org> - linux-clk <linux-clk@vger.kernel.org> - dri-devel <dri-devel@lists.freedesktop.org> - linux-sunxi <linux-sunxi@googlegroups.com> - " Icenowy Zheng <icenowy@aosc.io>\0" + "To\0Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\0" + "Cc\0Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>" + Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Mike Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Stephen Boyd <sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + David Airlie <airlied-cv59FeDIM0c@public.gmane.org> + Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> + devicetree <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-clk <linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + dri-devel <dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> + linux-sunxi <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> + " Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>\0" "\00:1\0" "b\0" "Dne sreda, 12. september 2018 ob 14:20:08 CEST je Chen-Yu Tsai napisal(a):\n" - "> On Wed, Sep 5, 2018 at 1:46 AM Jernej =C5=A0krabec <jernej.skrabec@siol.n=\n" - "et>=20\n" + "> On Wed, Sep 5, 2018 at 1:46 AM Jernej \305\240krabec <jernej.skrabec@siol.net> \n" "wrote:\n" - "> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(=\n" - "a):\n" - "> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.ne=\n" - "t>\n" - "> >=20\n" + "> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a):\n" + "> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec-ix9DCk4F938@public.gmane.orgt>\n" + "> > \n" "> > wrote:\n" "> > > > Support for mixer0, mixer1, writeback and rotation units is added.\n" - "> > > >=20\n" - "> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n" - "> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n" + "> > > > \n" + "> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>\n" + "> > > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>\n" "> > > > ---\n" - "> > > >=20\n" + "> > > > \n" "> > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65\n" "> > > > ++++++++++++++++++++++++++++\n" "> > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 +\n" "> > > > 2 files changed, 66 insertions(+)\n" - "> > > >=20\n" + "> > > > \n" "> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" "> > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index\n" "> > > > bae5ee67a797..4535c1c27d27\n" "> > > > 100644\n" "> > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" "> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" - "> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, \"bus-mixer1=\n" - "\",\n" + "> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, \"bus-mixer1\",\n" "> > > > \"bus-de\",>\n" - "> > > >=20\n" + "> > > > \n" "> > > > 0x04, BIT(1), 0);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_GATE(bus_wb_clk, \"bus-wb\", \"bus-de\",\n" - "> > > > =20\n" + "> > > > \n" "> > > > 0x04, BIT(2), 0);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_GATE(bus_rot_clk, \"bus-rot\", \"bus-de\",\n" "> > > > + 0x04, BIT(3), 0);\n" - "> > > >=20\n" - "> > > > static SUNXI_CCU_GATE(mixer0_clk, \"mixer0\", \"mixer0-div=\n" - "\",\n" - "> > > > =20\n" + "> > > > \n" + "> > > > static SUNXI_CCU_GATE(mixer0_clk, \"mixer0\", \"mixer0-div\",\n" + "> > > > \n" "> > > > 0x00, BIT(0), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, \"mixer1\",\n" "> > > > \"mixer1-div\",>\n" - "> > > >=20\n" + "> > > > \n" "> > > > 0x00, BIT(1), CLK_SET_RATE_PARENT);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_GATE(wb_clk, \"wb\", \"wb-div\",\n" - "> > > > =20\n" + "> > > > \n" "> > > > 0x00, BIT(2), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_GATE(rot_clk, \"rot\", \"rot-div\",\n" "> > > > + 0x00, BIT(3), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(mixer0_div_clk, \"mixer0-div\", \"de\", 0x0c, 0, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, \"mixer1-div\",\n" "> > > > \"de\",\n" "> > > > 0x0c, 4, 4,>\n" - "> > > >=20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(wb_div_clk, \"wb-div\", \"de\", 0x0c, 8, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_M(rot_div_clk, \"rot-div\", \"de\", 0x0c, 0x0c, 4,\n" "> > > > + CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" - "> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, \"mixer0-div\", \"pll-de\", 0x0=\n" - "c,\n" + "> > > > \n" + "> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, \"mixer0-div\", \"pll-de\", 0x0c,\n" "> > > > 0,\n" "> > > > 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk,\n" "> > > > \"mixer1-div\",\n" "> > > > \"pll-de\", 0x0c, 4, 4,>\n" - "> > > >=20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(wb_div_a83_clk, \"wb-div\", \"pll-de\", 0x0c, 8, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" - "> > > > +static struct ccu_common *sun50i_h6_de3_clks[] =3D {\n" + "> > > > \n" + "> > > > +static struct ccu_common *sun50i_h6_de3_clks[] = {\n" "> > > > + &mixer0_clk.common,\n" "> > > > + &mixer1_clk.common,\n" "> > > > + &wb_clk.common,\n" @@ -129,149 +124,142 @@ "> > > > + &rot_div_clk.common,\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static struct ccu_common *sun8i_a83t_de2_clks[] =3D {\n" - "> > > > =20\n" + "> > > > \n" + "> > > > static struct ccu_common *sun8i_a83t_de2_clks[] = {\n" + "> > > > \n" "> > > > &mixer0_clk.common,\n" "> > > > &mixer1_clk.common,\n" - "> > > >=20\n" - "> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] =\n" - "=3D {\n" - "> > > >=20\n" + "> > > > \n" + "> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {\n" + "> > > > \n" "> > > > &wb_div_clk.common,\n" - "> > > > =20\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks =3D {\n" - "> > > > + .hws =3D {\n" - "> > > > + [CLK_MIXER0] =3D &mixer0_clk.common.hw,\n" - "> > > > + [CLK_MIXER1] =3D &mixer1_clk.common.hw,\n" - "> > > > + [CLK_WB] =3D &wb_clk.common.hw,\n" - "> > > > + [CLK_ROT] =3D &rot_clk.common.hw,\n" + "> > > > \n" + "> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {\n" + "> > > > + .hws = {\n" + "> > > > + [CLK_MIXER0] = &mixer0_clk.common.hw,\n" + "> > > > + [CLK_MIXER1] = &mixer1_clk.common.hw,\n" + "> > > > + [CLK_WB] = &wb_clk.common.hw,\n" + "> > > > + [CLK_ROT] = &rot_clk.common.hw,\n" "> > > > +\n" - "> > > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_BUS_MIXER1] =3D &bus_mixer1_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_BUS_WB] =3D &bus_wb_clk.common.hw,\n" - "> > > > + [CLK_BUS_ROT] =3D &bus_rot_clk.common.hw,\n" + "> > > > + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,\n" + "> > > > + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,\n" + "> > > > + [CLK_BUS_WB] = &bus_wb_clk.common.hw,\n" + "> > > > + [CLK_BUS_ROT] = &bus_rot_clk.common.hw,\n" "> > > > +\n" - "> > > > + [CLK_MIXER0_DIV] =3D &mixer0_div_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_MIXER1_DIV] =3D &mixer1_div_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_WB_DIV] =3D &wb_div_clk.common.hw,\n" - "> > > > + [CLK_ROT_DIV] =3D &rot_div_clk.common.hw,\n" + "> > > > + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,\n" + "> > > > + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,\n" + "> > > > + [CLK_WB_DIV] = &wb_div_clk.common.hw,\n" + "> > > > + [CLK_ROT_DIV] = &rot_div_clk.common.hw,\n" "> > > > + },\n" - "> > > > + .num =3D 12,\n" - "> > >=20\n" + "> > > > + .num = 12,\n" + "> > > \n" "> > > It's best not to openly code these. It is error prone, like having\n" "> > > an index beyond .num, which then never gets registered.\n" - "> > >=20\n" + "> > > \n" "> > > Instead, please update CLK_NUMBERS and use that instead.\n" "> > > sunxi_ccu_probe()\n" "> > > can handle holes in .hws.\n" - "> >=20\n" - "> > I'm not sure this will work. All newly introduced indices are at the en=\n" - "d,\n" + "> > \n" + "> > I'm not sure this will work. All newly introduced indices are at the end,\n" "> > so other arrays will still have same length (hole at the end). You will\n" "> > just claim that arrays are larger than they really are, which means bad\n" "> > things.\n" - "> >=20\n" - "> > But I take any other suggestion. I really can't think of better solutio=\n" - "n.\n" - ">=20\n" + "> > \n" + "> > But I take any other suggestion. I really can't think of better solution.\n" + "> \n" "> Then maybe have macros for both cases instead?\n" "> CLK_NUMBER_WITH_ROT / CLK_NUMBER_WITHOUT_ROT?\n" "\n" - "That sounds reasonable. Do you want separate patch which renames original=20\n" + "That sounds reasonable. Do you want separate patch which renames original \n" "macro CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT?\n" "\n" "Best regards,\n" "Jernej\n" "\n" - ">=20\n" + "> \n" "> ChenYu\n" - ">=20\n" + "> \n" "> > Best regards,\n" "> > Jernej\n" - "> >=20\n" + "> > \n" "> > > On the other hand, it can't handle holes in the ccu_reset_map. Hope we\n" "> > > never have to deal with such an instance.\n" - "> > >=20\n" + "> > > \n" "> > > ChenYu\n" - "> > >=20\n" + "> > > \n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks =3D {\n" - "> > > > =20\n" - "> > > > .hws =3D {\n" - "> > > > =20\n" - "> > > > [CLK_MIXER0] =3D &mixer0_clk.common.hw,\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {\n" + "> > > > \n" + "> > > > .hws = {\n" + "> > > > \n" + "> > > > [CLK_MIXER0] = &mixer0_clk.common.hw,\n" + "> > > > \n" "> > > > @@ -156,6 +200,13 @@ static struct ccu_reset_map\n" - "> > > > sun50i_a64_de2_resets[] =3D\n" + "> > > > sun50i_a64_de2_resets[] =\n" "> > > > {>\n" - "> > > >=20\n" - "> > > > [RST_WB] =3D { 0x08, BIT(2) },\n" - "> > > > =20\n" + "> > > > \n" + "> > > > [RST_WB] = { 0x08, BIT(2) },\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] =3D {\n" - "> > > > + [RST_MIXER0] =3D { 0x08, BIT(0) },\n" - "> > > > + [RST_MIXER1] =3D { 0x08, BIT(1) },\n" - "> > > > + [RST_WB] =3D { 0x08, BIT(2) },\n" - "> > > > + [RST_ROT] =3D { 0x08, BIT(3) },\n" + "> > > > \n" + "> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] = {\n" + "> > > > + [RST_MIXER0] = { 0x08, BIT(0) },\n" + "> > > > + [RST_MIXER1] = { 0x08, BIT(1) },\n" + "> > > > + [RST_WB] = { 0x08, BIT(2) },\n" + "> > > > + [RST_ROT] = { 0x08, BIT(3) },\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc =3D {\n" - "> > > > =20\n" - "> > > > .ccu_clks =3D sun8i_a83t_de2_clks,\n" - "> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks),\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {\n" + "> > > > \n" + "> > > > .ccu_clks = sun8i_a83t_de2_clks,\n" + "> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),\n" + "> > > > \n" "> > > > @@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc\n" - "> > > > sun50i_a64_de2_clk_desc =3D {>\n" - "> > > >=20\n" - "> > > > .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets),\n" - "> > > > =20\n" + "> > > > sun50i_a64_de2_clk_desc = {>\n" + "> > > > \n" + "> > > > .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc =3D {\n" - "> > > > + .ccu_clks =3D sun50i_h6_de3_clks,\n" - "> > > > + .num_ccu_clks =3D ARRAY_SIZE(sun50i_h6_de3_clks),\n" + "> > > > \n" + "> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {\n" + "> > > > + .ccu_clks = sun50i_h6_de3_clks,\n" + "> > > > + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),\n" "> > > > +\n" - "> > > > + .hw_clks =3D &sun50i_h6_de3_hw_clks,\n" + "> > > > + .hw_clks = &sun50i_h6_de3_hw_clks,\n" "> > > > +\n" - "> > > > + .resets =3D sun50i_h6_de3_resets,\n" - "> > > > + .num_resets =3D ARRAY_SIZE(sun50i_h6_de3_resets),\n" + "> > > > + .resets = sun50i_h6_de3_resets,\n" + "> > > > + .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc =3D {\n" - "> > > > =20\n" - "> > > > .ccu_clks =3D sun8i_v3s_de2_clks,\n" - "> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_v3s_de2_clks),\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {\n" + "> > > > \n" + "> > > > .ccu_clks = sun8i_v3s_de2_clks,\n" + "> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),\n" + "> > > > \n" "> > > > @@ -296,6 +357,10 @@ static const struct of_device_id\n" "> > > > sunxi_de2_clk_ids[]\n" - "> > > > =3D {>\n" - "> > > >=20\n" - "> > > > .compatible =3D \"allwinner,sun50i-h5-de2-clk\",\n" - "> > > > .data =3D &sun50i_a64_de2_clk_desc,\n" - "> > > > =20\n" + "> > > > = {>\n" + "> > > > \n" + "> > > > .compatible = \"allwinner,sun50i-h5-de2-clk\",\n" + "> > > > .data = &sun50i_a64_de2_clk_desc,\n" + "> > > > \n" "> > > > },\n" - "> > > >=20\n" + "> > > > \n" "> > > > + {\n" - "> > > > + .compatible =3D \"allwinner,sun50i-h6-de3-clk\",\n" - "> > > > + .data =3D &sun50i_h6_de3_clk_desc,\n" + "> > > > + .compatible = \"allwinner,sun50i-h6-de3-clk\",\n" + "> > > > + .data = &sun50i_h6_de3_clk_desc,\n" "> > > > + },\n" - "> > > >=20\n" + "> > > > \n" "> > > > { }\n" - "> > > > =20\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" + "> > > > \n" "> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h index\n" "> > > > 530c006e0ae9..27bd88539f42\n" @@ -279,16 +267,24 @@ "> > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > @@ -22,6 +22,7 @@\n" - "> > > >=20\n" + "> > > > \n" "> > > > #define CLK_MIXER0_DIV 3\n" "> > > > #define CLK_MIXER1_DIV 4\n" "> > > > #define CLK_WB_DIV 5\n" - "> > > >=20\n" + "> > > > \n" "> > > > +#define CLK_ROT_DIV 11\n" - "> > > >=20\n" + "> > > > \n" "> > > > #define CLK_NUMBER (CLK_WB + 1)\n" - "> > > >=20\n" + "> > > > \n" "> > > > --\n" - > > > > 2.18.0 + "> > > > 2.18.0\n" + "\n" + "\n" + "\n" + "\n" + "-- \n" + "You received this message because you are subscribed to the Google Groups \"linux-sunxi\" group.\n" + "To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org\n" + For more options, visit https://groups.google.com/d/optout. -66dcf48964934fd7e865d8cdad6a01d8b0ecaa1a81ea2efc61ecbd02da2d8a40 +11e0c970919355a1c3797ce4192233a3818d3c639cac96fdae15610850213b83
diff --git a/a/1.txt b/N3/1.txt index 2070f87..e0866a4 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,93 +1,87 @@ Dne sreda, 12. september 2018 ob 14:20:08 CEST je Chen-Yu Tsai napisal(a): -> On Wed, Sep 5, 2018 at 1:46 AM Jernej =C5=A0krabec <jernej.skrabec@siol.n= -et>=20 +> On Wed, Sep 5, 2018 at 1:46 AM Jernej Škrabec <jernej.skrabec@siol.net> wrote: -> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(= -a): -> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.ne= -t> -> >=20 +> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a): +> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.net> +> > > > wrote: > > > > Support for mixer0, mixer1, writeback and rotation units is added. -> > > >=20 +> > > > > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > > --- -> > > >=20 +> > > > > > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65 > > > > ++++++++++++++++++++++++++++ > > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 + > > > > 2 files changed, 66 insertions(+) -> > > >=20 +> > > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index > > > > bae5ee67a797..4535c1c27d27 > > > > 100644 > > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c -> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1= -", +> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", > > > > "bus-de",> -> > > >=20 +> > > > > > > > 0x04, BIT(1), 0); -> > > > =20 +> > > > > > > > static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de", -> > > > =20 +> > > > > > > > 0x04, BIT(2), 0); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de", > > > > + 0x04, BIT(3), 0); -> > > >=20 -> > > > static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div= -", -> > > > =20 +> > > > +> > > > static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div", +> > > > > > > > 0x00, BIT(0), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, "mixer1", > > > > "mixer1-div",> -> > > >=20 +> > > > > > > > 0x00, BIT(1), CLK_SET_RATE_PARENT); -> > > > =20 +> > > > > > > > static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", -> > > > =20 +> > > > > > > > 0x00, BIT(2), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div", > > > > + 0x00, BIT(3), CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", > > > > "de", > > > > 0x0c, 4, 4,> -> > > >=20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > > =20 +> > > > > > > > static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > +static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4, > > > > + CLK_SET_RATE_PARENT); -> > > >=20 -> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0= -c, +> > > > +> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, > > > > 0, > > > > 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 +> > > > > > > > @@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, > > > > "mixer1-div", > > > > "pll-de", 0x0c, 4, 4,> -> > > >=20 +> > > > > > > > static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, -> > > > =20 +> > > > > > > > CLK_SET_RATE_PARENT); -> > > >=20 -> > > > +static struct ccu_common *sun50i_h6_de3_clks[] =3D { +> > > > +> > > > +static struct ccu_common *sun50i_h6_de3_clks[] = { > > > > + &mixer0_clk.common, > > > > + &mixer1_clk.common, > > > > + &wb_clk.common, @@ -105,149 +99,142 @@ c, > > > > + &rot_div_clk.common, > > > > +}; > > > > + -> > > >=20 -> > > > static struct ccu_common *sun8i_a83t_de2_clks[] =3D { -> > > > =20 +> > > > +> > > > static struct ccu_common *sun8i_a83t_de2_clks[] = { +> > > > > > > > &mixer0_clk.common, > > > > &mixer1_clk.common, -> > > >=20 -> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = -=3D { -> > > >=20 +> > > > +> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = { +> > > > > > > > &wb_div_clk.common, -> > > > =20 +> > > > > > > > }; -> > > >=20 -> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks =3D { -> > > > + .hws =3D { -> > > > + [CLK_MIXER0] =3D &mixer0_clk.common.hw, -> > > > + [CLK_MIXER1] =3D &mixer1_clk.common.hw, -> > > > + [CLK_WB] =3D &wb_clk.common.hw, -> > > > + [CLK_ROT] =3D &rot_clk.common.hw, +> > > > +> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = { +> > > > + .hws = { +> > > > + [CLK_MIXER0] = &mixer0_clk.common.hw, +> > > > + [CLK_MIXER1] = &mixer1_clk.common.hw, +> > > > + [CLK_WB] = &wb_clk.common.hw, +> > > > + [CLK_ROT] = &rot_clk.common.hw, > > > > + -> > > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_clk.common.= -hw, -> > > > + [CLK_BUS_MIXER1] =3D &bus_mixer1_clk.common.= -hw, -> > > > + [CLK_BUS_WB] =3D &bus_wb_clk.common.hw, -> > > > + [CLK_BUS_ROT] =3D &bus_rot_clk.common.hw, +> > > > + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, +> > > > + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, +> > > > + [CLK_BUS_WB] = &bus_wb_clk.common.hw, +> > > > + [CLK_BUS_ROT] = &bus_rot_clk.common.hw, > > > > + -> > > > + [CLK_MIXER0_DIV] =3D &mixer0_div_clk.common.= -hw, -> > > > + [CLK_MIXER1_DIV] =3D &mixer1_div_clk.common.= -hw, -> > > > + [CLK_WB_DIV] =3D &wb_div_clk.common.hw, -> > > > + [CLK_ROT_DIV] =3D &rot_div_clk.common.hw, +> > > > + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, +> > > > + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, +> > > > + [CLK_WB_DIV] = &wb_div_clk.common.hw, +> > > > + [CLK_ROT_DIV] = &rot_div_clk.common.hw, > > > > + }, -> > > > + .num =3D 12, -> > >=20 +> > > > + .num = 12, +> > > > > > It's best not to openly code these. It is error prone, like having > > > an index beyond .num, which then never gets registered. -> > >=20 +> > > > > > Instead, please update CLK_NUMBERS and use that instead. > > > sunxi_ccu_probe() > > > can handle holes in .hws. -> >=20 -> > I'm not sure this will work. All newly introduced indices are at the en= -d, +> > +> > I'm not sure this will work. All newly introduced indices are at the end, > > so other arrays will still have same length (hole at the end). You will > > just claim that arrays are larger than they really are, which means bad > > things. -> >=20 -> > But I take any other suggestion. I really can't think of better solutio= -n. ->=20 +> > +> > But I take any other suggestion. I really can't think of better solution. +> > Then maybe have macros for both cases instead? > CLK_NUMBER_WITH_ROT / CLK_NUMBER_WITHOUT_ROT? -That sounds reasonable. Do you want separate patch which renames original=20 +That sounds reasonable. Do you want separate patch which renames original macro CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT? Best regards, Jernej ->=20 +> > ChenYu ->=20 +> > > Best regards, > > Jernej -> >=20 +> > > > > On the other hand, it can't handle holes in the ccu_reset_map. Hope we > > > never have to deal with such an instance. -> > >=20 +> > > > > > ChenYu -> > >=20 +> > > > > > > +}; > > > > + -> > > >=20 -> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks =3D { -> > > > =20 -> > > > .hws =3D { -> > > > =20 -> > > > [CLK_MIXER0] =3D &mixer0_clk.common.hw, -> > > >=20 +> > > > +> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { +> > > > +> > > > .hws = { +> > > > +> > > > [CLK_MIXER0] = &mixer0_clk.common.hw, +> > > > > > > > @@ -156,6 +200,13 @@ static struct ccu_reset_map -> > > > sun50i_a64_de2_resets[] =3D +> > > > sun50i_a64_de2_resets[] = > > > > {> -> > > >=20 -> > > > [RST_WB] =3D { 0x08, BIT(2) }, -> > > > =20 +> > > > +> > > > [RST_WB] = { 0x08, BIT(2) }, +> > > > > > > > }; -> > > >=20 -> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] =3D { -> > > > + [RST_MIXER0] =3D { 0x08, BIT(0) }, -> > > > + [RST_MIXER1] =3D { 0x08, BIT(1) }, -> > > > + [RST_WB] =3D { 0x08, BIT(2) }, -> > > > + [RST_ROT] =3D { 0x08, BIT(3) }, +> > > > +> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] = { +> > > > + [RST_MIXER0] = { 0x08, BIT(0) }, +> > > > + [RST_MIXER1] = { 0x08, BIT(1) }, +> > > > + [RST_WB] = { 0x08, BIT(2) }, +> > > > + [RST_ROT] = { 0x08, BIT(3) }, > > > > +}; > > > > + -> > > >=20 -> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc =3D { -> > > > =20 -> > > > .ccu_clks =3D sun8i_a83t_de2_clks, -> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks), -> > > >=20 +> > > > +> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { +> > > > +> > > > .ccu_clks = sun8i_a83t_de2_clks, +> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), +> > > > > > > > @@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc -> > > > sun50i_a64_de2_clk_desc =3D {> -> > > >=20 -> > > > .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets), -> > > > =20 +> > > > sun50i_a64_de2_clk_desc = {> +> > > > +> > > > .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), +> > > > > > > > }; -> > > >=20 -> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc =3D { -> > > > + .ccu_clks =3D sun50i_h6_de3_clks, -> > > > + .num_ccu_clks =3D ARRAY_SIZE(sun50i_h6_de3_clks), +> > > > +> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = { +> > > > + .ccu_clks = sun50i_h6_de3_clks, +> > > > + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks), > > > > + -> > > > + .hw_clks =3D &sun50i_h6_de3_hw_clks, +> > > > + .hw_clks = &sun50i_h6_de3_hw_clks, > > > > + -> > > > + .resets =3D sun50i_h6_de3_resets, -> > > > + .num_resets =3D ARRAY_SIZE(sun50i_h6_de3_resets), +> > > > + .resets = sun50i_h6_de3_resets, +> > > > + .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets), > > > > +}; > > > > + -> > > >=20 -> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc =3D { -> > > > =20 -> > > > .ccu_clks =3D sun8i_v3s_de2_clks, -> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_v3s_de2_clks), -> > > >=20 +> > > > +> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { +> > > > +> > > > .ccu_clks = sun8i_v3s_de2_clks, +> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), +> > > > > > > > @@ -296,6 +357,10 @@ static const struct of_device_id > > > > sunxi_de2_clk_ids[] -> > > > =3D {> -> > > >=20 -> > > > .compatible =3D "allwinner,sun50i-h5-de2-clk", -> > > > .data =3D &sun50i_a64_de2_clk_desc, -> > > > =20 +> > > > = {> +> > > > +> > > > .compatible = "allwinner,sun50i-h5-de2-clk", +> > > > .data = &sun50i_a64_de2_clk_desc, +> > > > > > > > }, -> > > >=20 +> > > > > > > > + { -> > > > + .compatible =3D "allwinner,sun50i-h6-de3-clk", -> > > > + .data =3D &sun50i_h6_de3_clk_desc, +> > > > + .compatible = "allwinner,sun50i-h6-de3-clk", +> > > > + .data = &sun50i_h6_de3_clk_desc, > > > > + }, -> > > >=20 +> > > > > > > > { } -> > > > =20 +> > > > > > > > }; -> > > >=20 +> > > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h index > > > > 530c006e0ae9..27bd88539f42 @@ -255,14 +242,14 @@ Jernej > > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h > > > > @@ -22,6 +22,7 @@ -> > > >=20 +> > > > > > > > #define CLK_MIXER0_DIV 3 > > > > #define CLK_MIXER1_DIV 4 > > > > #define CLK_WB_DIV 5 -> > > >=20 +> > > > > > > > +#define CLK_ROT_DIV 11 -> > > >=20 +> > > > > > > > #define CLK_NUMBER (CLK_WB + 1) -> > > >=20 +> > > > > > > > -- > > > > 2.18.0 diff --git a/a/content_digest b/N3/content_digest index 0af2ffe..cdd4406 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -23,95 +23,89 @@ "\00:1\0" "b\0" "Dne sreda, 12. september 2018 ob 14:20:08 CEST je Chen-Yu Tsai napisal(a):\n" - "> On Wed, Sep 5, 2018 at 1:46 AM Jernej =C5=A0krabec <jernej.skrabec@siol.n=\n" - "et>=20\n" + "> On Wed, Sep 5, 2018 at 1:46 AM Jernej \305\240krabec <jernej.skrabec@siol.net> \n" "wrote:\n" - "> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(=\n" - "a):\n" - "> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.ne=\n" - "t>\n" - "> >=20\n" + "> > Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a):\n" + "> > > On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@siol.net>\n" + "> > \n" "> > wrote:\n" "> > > > Support for mixer0, mixer1, writeback and rotation units is added.\n" - "> > > >=20\n" + "> > > > \n" "> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n" "> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n" "> > > > ---\n" - "> > > >=20\n" + "> > > > \n" "> > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65\n" "> > > > ++++++++++++++++++++++++++++\n" "> > > > drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 1 +\n" "> > > > 2 files changed, 66 insertions(+)\n" - "> > > >=20\n" + "> > > > \n" "> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" "> > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index\n" "> > > > bae5ee67a797..4535c1c27d27\n" "> > > > 100644\n" "> > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" "> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c\n" - "> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, \"bus-mixer1=\n" - "\",\n" + "> > > > @@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, \"bus-mixer1\",\n" "> > > > \"bus-de\",>\n" - "> > > >=20\n" + "> > > > \n" "> > > > 0x04, BIT(1), 0);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_GATE(bus_wb_clk, \"bus-wb\", \"bus-de\",\n" - "> > > > =20\n" + "> > > > \n" "> > > > 0x04, BIT(2), 0);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_GATE(bus_rot_clk, \"bus-rot\", \"bus-de\",\n" "> > > > + 0x04, BIT(3), 0);\n" - "> > > >=20\n" - "> > > > static SUNXI_CCU_GATE(mixer0_clk, \"mixer0\", \"mixer0-div=\n" - "\",\n" - "> > > > =20\n" + "> > > > \n" + "> > > > static SUNXI_CCU_GATE(mixer0_clk, \"mixer0\", \"mixer0-div\",\n" + "> > > > \n" "> > > > 0x00, BIT(0), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, \"mixer1\",\n" "> > > > \"mixer1-div\",>\n" - "> > > >=20\n" + "> > > > \n" "> > > > 0x00, BIT(1), CLK_SET_RATE_PARENT);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_GATE(wb_clk, \"wb\", \"wb-div\",\n" - "> > > > =20\n" + "> > > > \n" "> > > > 0x00, BIT(2), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_GATE(rot_clk, \"rot\", \"rot-div\",\n" "> > > > + 0x00, BIT(3), CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(mixer0_div_clk, \"mixer0-div\", \"de\", 0x0c, 0, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, \"mixer1-div\",\n" "> > > > \"de\",\n" "> > > > 0x0c, 4, 4,>\n" - "> > > >=20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > > =20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(wb_div_clk, \"wb-div\", \"de\", 0x0c, 8, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > +static SUNXI_CCU_M(rot_div_clk, \"rot-div\", \"de\", 0x0c, 0x0c, 4,\n" "> > > > + CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" - "> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, \"mixer0-div\", \"pll-de\", 0x0=\n" - "c,\n" + "> > > > \n" + "> > > > static SUNXI_CCU_M(mixer0_div_a83_clk, \"mixer0-div\", \"pll-de\", 0x0c,\n" "> > > > 0,\n" "> > > > 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" + "> > > > \n" "> > > > @@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk,\n" "> > > > \"mixer1-div\",\n" "> > > > \"pll-de\", 0x0c, 4, 4,>\n" - "> > > >=20\n" + "> > > > \n" "> > > > static SUNXI_CCU_M(wb_div_a83_clk, \"wb-div\", \"pll-de\", 0x0c, 8, 4,\n" - "> > > > =20\n" + "> > > > \n" "> > > > CLK_SET_RATE_PARENT);\n" - "> > > >=20\n" - "> > > > +static struct ccu_common *sun50i_h6_de3_clks[] =3D {\n" + "> > > > \n" + "> > > > +static struct ccu_common *sun50i_h6_de3_clks[] = {\n" "> > > > + &mixer0_clk.common,\n" "> > > > + &mixer1_clk.common,\n" "> > > > + &wb_clk.common,\n" @@ -129,149 +123,142 @@ "> > > > + &rot_div_clk.common,\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static struct ccu_common *sun8i_a83t_de2_clks[] =3D {\n" - "> > > > =20\n" + "> > > > \n" + "> > > > static struct ccu_common *sun8i_a83t_de2_clks[] = {\n" + "> > > > \n" "> > > > &mixer0_clk.common,\n" "> > > > &mixer1_clk.common,\n" - "> > > >=20\n" - "> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] =\n" - "=3D {\n" - "> > > >=20\n" + "> > > > \n" + "> > > > @@ -92,6 +116,26 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {\n" + "> > > > \n" "> > > > &wb_div_clk.common,\n" - "> > > > =20\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks =3D {\n" - "> > > > + .hws =3D {\n" - "> > > > + [CLK_MIXER0] =3D &mixer0_clk.common.hw,\n" - "> > > > + [CLK_MIXER1] =3D &mixer1_clk.common.hw,\n" - "> > > > + [CLK_WB] =3D &wb_clk.common.hw,\n" - "> > > > + [CLK_ROT] =3D &rot_clk.common.hw,\n" + "> > > > \n" + "> > > > +static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {\n" + "> > > > + .hws = {\n" + "> > > > + [CLK_MIXER0] = &mixer0_clk.common.hw,\n" + "> > > > + [CLK_MIXER1] = &mixer1_clk.common.hw,\n" + "> > > > + [CLK_WB] = &wb_clk.common.hw,\n" + "> > > > + [CLK_ROT] = &rot_clk.common.hw,\n" "> > > > +\n" - "> > > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_BUS_MIXER1] =3D &bus_mixer1_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_BUS_WB] =3D &bus_wb_clk.common.hw,\n" - "> > > > + [CLK_BUS_ROT] =3D &bus_rot_clk.common.hw,\n" + "> > > > + [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,\n" + "> > > > + [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,\n" + "> > > > + [CLK_BUS_WB] = &bus_wb_clk.common.hw,\n" + "> > > > + [CLK_BUS_ROT] = &bus_rot_clk.common.hw,\n" "> > > > +\n" - "> > > > + [CLK_MIXER0_DIV] =3D &mixer0_div_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_MIXER1_DIV] =3D &mixer1_div_clk.common.=\n" - "hw,\n" - "> > > > + [CLK_WB_DIV] =3D &wb_div_clk.common.hw,\n" - "> > > > + [CLK_ROT_DIV] =3D &rot_div_clk.common.hw,\n" + "> > > > + [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,\n" + "> > > > + [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,\n" + "> > > > + [CLK_WB_DIV] = &wb_div_clk.common.hw,\n" + "> > > > + [CLK_ROT_DIV] = &rot_div_clk.common.hw,\n" "> > > > + },\n" - "> > > > + .num =3D 12,\n" - "> > >=20\n" + "> > > > + .num = 12,\n" + "> > > \n" "> > > It's best not to openly code these. It is error prone, like having\n" "> > > an index beyond .num, which then never gets registered.\n" - "> > >=20\n" + "> > > \n" "> > > Instead, please update CLK_NUMBERS and use that instead.\n" "> > > sunxi_ccu_probe()\n" "> > > can handle holes in .hws.\n" - "> >=20\n" - "> > I'm not sure this will work. All newly introduced indices are at the en=\n" - "d,\n" + "> > \n" + "> > I'm not sure this will work. All newly introduced indices are at the end,\n" "> > so other arrays will still have same length (hole at the end). You will\n" "> > just claim that arrays are larger than they really are, which means bad\n" "> > things.\n" - "> >=20\n" - "> > But I take any other suggestion. I really can't think of better solutio=\n" - "n.\n" - ">=20\n" + "> > \n" + "> > But I take any other suggestion. I really can't think of better solution.\n" + "> \n" "> Then maybe have macros for both cases instead?\n" "> CLK_NUMBER_WITH_ROT / CLK_NUMBER_WITHOUT_ROT?\n" "\n" - "That sounds reasonable. Do you want separate patch which renames original=20\n" + "That sounds reasonable. Do you want separate patch which renames original \n" "macro CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT?\n" "\n" "Best regards,\n" "Jernej\n" "\n" - ">=20\n" + "> \n" "> ChenYu\n" - ">=20\n" + "> \n" "> > Best regards,\n" "> > Jernej\n" - "> >=20\n" + "> > \n" "> > > On the other hand, it can't handle holes in the ccu_reset_map. Hope we\n" "> > > never have to deal with such an instance.\n" - "> > >=20\n" + "> > > \n" "> > > ChenYu\n" - "> > >=20\n" + "> > > \n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks =3D {\n" - "> > > > =20\n" - "> > > > .hws =3D {\n" - "> > > > =20\n" - "> > > > [CLK_MIXER0] =3D &mixer0_clk.common.hw,\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {\n" + "> > > > \n" + "> > > > .hws = {\n" + "> > > > \n" + "> > > > [CLK_MIXER0] = &mixer0_clk.common.hw,\n" + "> > > > \n" "> > > > @@ -156,6 +200,13 @@ static struct ccu_reset_map\n" - "> > > > sun50i_a64_de2_resets[] =3D\n" + "> > > > sun50i_a64_de2_resets[] =\n" "> > > > {>\n" - "> > > >=20\n" - "> > > > [RST_WB] =3D { 0x08, BIT(2) },\n" - "> > > > =20\n" + "> > > > \n" + "> > > > [RST_WB] = { 0x08, BIT(2) },\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] =3D {\n" - "> > > > + [RST_MIXER0] =3D { 0x08, BIT(0) },\n" - "> > > > + [RST_MIXER1] =3D { 0x08, BIT(1) },\n" - "> > > > + [RST_WB] =3D { 0x08, BIT(2) },\n" - "> > > > + [RST_ROT] =3D { 0x08, BIT(3) },\n" + "> > > > \n" + "> > > > +static struct ccu_reset_map sun50i_h6_de3_resets[] = {\n" + "> > > > + [RST_MIXER0] = { 0x08, BIT(0) },\n" + "> > > > + [RST_MIXER1] = { 0x08, BIT(1) },\n" + "> > > > + [RST_WB] = { 0x08, BIT(2) },\n" + "> > > > + [RST_ROT] = { 0x08, BIT(3) },\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc =3D {\n" - "> > > > =20\n" - "> > > > .ccu_clks =3D sun8i_a83t_de2_clks,\n" - "> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks),\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {\n" + "> > > > \n" + "> > > > .ccu_clks = sun8i_a83t_de2_clks,\n" + "> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),\n" + "> > > > \n" "> > > > @@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc\n" - "> > > > sun50i_a64_de2_clk_desc =3D {>\n" - "> > > >=20\n" - "> > > > .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets),\n" - "> > > > =20\n" + "> > > > sun50i_a64_de2_clk_desc = {>\n" + "> > > > \n" + "> > > > .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" - "> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc =3D {\n" - "> > > > + .ccu_clks =3D sun50i_h6_de3_clks,\n" - "> > > > + .num_ccu_clks =3D ARRAY_SIZE(sun50i_h6_de3_clks),\n" + "> > > > \n" + "> > > > +static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {\n" + "> > > > + .ccu_clks = sun50i_h6_de3_clks,\n" + "> > > > + .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),\n" "> > > > +\n" - "> > > > + .hw_clks =3D &sun50i_h6_de3_hw_clks,\n" + "> > > > + .hw_clks = &sun50i_h6_de3_hw_clks,\n" "> > > > +\n" - "> > > > + .resets =3D sun50i_h6_de3_resets,\n" - "> > > > + .num_resets =3D ARRAY_SIZE(sun50i_h6_de3_resets),\n" + "> > > > + .resets = sun50i_h6_de3_resets,\n" + "> > > > + .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),\n" "> > > > +};\n" "> > > > +\n" - "> > > >=20\n" - "> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc =3D {\n" - "> > > > =20\n" - "> > > > .ccu_clks =3D sun8i_v3s_de2_clks,\n" - "> > > > .num_ccu_clks =3D ARRAY_SIZE(sun8i_v3s_de2_clks),\n" - "> > > >=20\n" + "> > > > \n" + "> > > > static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {\n" + "> > > > \n" + "> > > > .ccu_clks = sun8i_v3s_de2_clks,\n" + "> > > > .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),\n" + "> > > > \n" "> > > > @@ -296,6 +357,10 @@ static const struct of_device_id\n" "> > > > sunxi_de2_clk_ids[]\n" - "> > > > =3D {>\n" - "> > > >=20\n" - "> > > > .compatible =3D \"allwinner,sun50i-h5-de2-clk\",\n" - "> > > > .data =3D &sun50i_a64_de2_clk_desc,\n" - "> > > > =20\n" + "> > > > = {>\n" + "> > > > \n" + "> > > > .compatible = \"allwinner,sun50i-h5-de2-clk\",\n" + "> > > > .data = &sun50i_a64_de2_clk_desc,\n" + "> > > > \n" "> > > > },\n" - "> > > >=20\n" + "> > > > \n" "> > > > + {\n" - "> > > > + .compatible =3D \"allwinner,sun50i-h6-de3-clk\",\n" - "> > > > + .data =3D &sun50i_h6_de3_clk_desc,\n" + "> > > > + .compatible = \"allwinner,sun50i-h6-de3-clk\",\n" + "> > > > + .data = &sun50i_h6_de3_clk_desc,\n" "> > > > + },\n" - "> > > >=20\n" + "> > > > \n" "> > > > { }\n" - "> > > > =20\n" + "> > > > \n" "> > > > };\n" - "> > > >=20\n" + "> > > > \n" "> > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h index\n" "> > > > 530c006e0ae9..27bd88539f42\n" @@ -279,16 +266,16 @@ "> > > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h\n" "> > > > @@ -22,6 +22,7 @@\n" - "> > > >=20\n" + "> > > > \n" "> > > > #define CLK_MIXER0_DIV 3\n" "> > > > #define CLK_MIXER1_DIV 4\n" "> > > > #define CLK_WB_DIV 5\n" - "> > > >=20\n" + "> > > > \n" "> > > > +#define CLK_ROT_DIV 11\n" - "> > > >=20\n" + "> > > > \n" "> > > > #define CLK_NUMBER (CLK_WB + 1)\n" - "> > > >=20\n" + "> > > > \n" "> > > > --\n" > > > > 2.18.0 -66dcf48964934fd7e865d8cdad6a01d8b0ecaa1a81ea2efc61ecbd02da2d8a40 +35751c252ac98d9640ca3cf8c09909a51245d429c888fe89e6fcf98707fee3a5
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