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Fri, 15 May 2026 12:54:49 -0700 (PDT) X-Received: by 2002:a05:620a:698a:b0:8cd:8884:2509 with SMTP id af79cd13be357-911cf2f0e0cmr890113485a.55.1778874888666; Fri, 15 May 2026 12:54:48 -0700 (PDT) Received: from [192.168.68.106] ([191.202.238.222]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8c908562931sm61375056d6.3.2026.05.15.12.54.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 12:54:48 -0700 (PDT) Message-ID: <174f03b2-b979-47d2-aec8-645d797ab758@oss.qualcomm.com> Date: Fri, 15 May 2026 16:54:43 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/4] target/riscv: Add server platform reference cpu To: Nicholas Piggin Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, leif.lindholm@oss.qualcomm.com, andrew.jones@oss.qualcomm.com, Fei Wu References: <20260514204640.2540054-1-daniel.barboza@oss.qualcomm.com> <20260514204640.2540054-3-daniel.barboza@oss.qualcomm.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/15/2026 3:15 PM, Nicholas Piggin wrote: > On Thu, May 14, 2026 at 05:46:38PM -0300, Daniel Henrique Barboza wrote: >> From: Fei Wu >> >> The harts requirements of RISC-V server platform [1] require RVA23 ISA >> profile support and others. >> >> This patch provides a new "riscv-server-ref" CPU to go along with the >> future "riscv-server-ref" board. > > About compatibility, if we get a server platform spec v2.0 that requires > a different machine and RVA28 + Sxxx CPU. Is the plan to update these, > or add a new CPU and machine types? If the latter, then perhaps a > version in the names like riscv-server-v1.0 / riscv-server-v1.0-cpu > would be good. Good question. We can get away with machine props to change the board behavior based on spec version but not sure if this makes sense with a CPU. I suppose we could live with: -cpu riscv-server-ref,spec1.1=on to change the CPU setup to v1.1 and so on, but creating a new CPU with the spec version in the name like you suggested (e.g. riscv-server-ref-v1.1) seems cleaner. In particular if the spec doesn't change that much - which I guess it's fair to assume given that a reference spec wouldn't be much of a reference if it keeps changing/updating all the time ... Thanks, Daniel > > Non-versioned names could be aliases to the latest one, but I don't know > if that is really worthwhile particularly for non virtualized system. > > Thanks, > Nick