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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by SA1PR11MB8320.namprd11.prod.outlook.com (2603:10b6:806:37c::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.14; Fri, 31 Oct 2025 02:48:59 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.9275.013; Fri, 31 Oct 2025 02:48:59 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20251029212215.GC2806654@mdroper-desk1.amr.corp.intel.com> References: <20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com> <20251021-xe3p_lpd-basic-enabling-v2-13-10eae6d655b8@intel.com> <20251029212215.GC2806654@mdroper-desk1.amr.corp.intel.com> Subject: Re: [PATCH v2 13/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers From: Gustavo Sousa CC: , , "Ankit Nautiyal" , Dnyaneshwar Bhadane , Jouni =?utf-8?q?H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Ravi Kumar Vodapalli , Shekhar Chauhan , Vinod Govindapillai , Jani Nikula To: Matt Roper Date: Thu, 30 Oct 2025 23:48:55 -0300 Message-ID: <176187893526.3303.4396397116272962497@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: BY5PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:1e0::19) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|SA1PR11MB8320:EE_ X-MS-Office365-Filtering-Correlation-Id: b86a01a5-967c-4adb-d9be-08de18280a84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016; 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Update the changed fields in the driver. >> Below are the changes: >>=20 >> MBUS_CTL: >> Translation Throttle Min >> It changed from BIT[15:13] to BIT[16:13] >>=20 >> DBUF_CTL: >> Min Tracker State Service >> It changed from BIT[18:16] to BIT[20:16] >> Max Tracker State Service >> It changed to from BIT[23:19] to BIT[14:10] >> but using default value, so no need to define >> in code. > >In a lot of cases when a register field picks up extra high bit(s), the >extra bits were previously reserved, so it's fine to just adjust the >existing definition (since reserved bits are required to always read out >of hardware as zeroes). However in these cases, the new bits these >fields are extending into were actively used by the hardware for other >purposes on previous platforms, which is why it's necessary to keep the >existing pre-Xe3p definitions unchanged and create separate Xe3p ones >that can be used only on the newer Xe3p platforms. You should make some >mention of that in the commit message so it's clear why we're handling >these a bit differently than a lot of other registers. Agreed. Just updated the local v3 to make that clear. > >>=20 >> v2: >> - Keep definitions in the same line (i.e. without line continuation >> breaks) for better readability. (Jani) >>=20 >> Bspec: 68868, 68872 >> Cc: Jani Nikula >> Signed-off-by: Ravi Kumar Vodapalli >> Signed-off-by: Gustavo Sousa >> --- >> drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++++-- >> drivers/gpu/drm/i915/display/skl_watermark_regs.h | 52 ++++++++++++----= ------- >> 2 files changed, 40 insertions(+), 28 deletions(-) >>=20 >> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/= drm/i915/display/skl_watermark.c >> index 256162da9afc..c141d575009f 100644 >> --- a/drivers/gpu/drm/i915/display/skl_watermark.c >> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c >> @@ -3477,7 +3477,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct i= ntel_display *display, >> if (!HAS_MBUS_JOINING(display)) >> return; >> =20 >> - if (DISPLAY_VER(display) >=3D 20) >> + if (DISPLAY_VER(display) >=3D 35) >> + intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_T= HROTTLE_MIN_MASK, >> + XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio -= 1)); >> + else if (DISPLAY_VER(display) >=3D 20) >> intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTT= LE_MIN_MASK, >> MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); >> =20 >> @@ -3488,9 +3491,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct i= ntel_display *display, >> ratio, str_yes_no(joined_mbus)); >> =20 >> for_each_dbuf_slice(display, slice) >> - intel_de_rmw(display, DBUF_CTL_S(slice), >> - DBUF_MIN_TRACKER_STATE_SERVICE_MASK, >> - DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1))= ; >> + if (DISPLAY_VER(display) >=3D 35) >> + intel_de_rmw(display, DBUF_CTL_S(slice), >> + XE3P_DBUF_MIN_TRACKER_STATE_SERVIC= E_MASK, >> + XE3P_DBUF_MIN_TRACKER_STATE_SERVIC= E(ratio - 1)); >> + else >> + intel_de_rmw(display, DBUF_CTL_S(slice), >> + DBUF_MIN_TRACKER_STATE_SERVICE_MAS= K, >> + DBUF_MIN_TRACKER_STATE_SERVICE(rat= io - 1)); >> } >> =20 >> static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_sta= te *state) >> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers= /gpu/drm/i915/display/skl_watermark_regs.h >> index c5572fc0e847..94915afc6b0b 100644 >> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h >> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h >> @@ -32,16 +32,18 @@ >> #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) >> #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) >> =20 >> -#define MBUS_CTL _MMIO(0x4438C) >> -#define MBUS_JOIN REG_BIT(31) >> -#define MBUS_HASHING_MODE_MASK REG_BIT(30) >> -#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(M= BUS_HASHING_MODE_MASK, 0) >> -#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(M= BUS_HASHING_MODE_MASK, 1) >> -#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) >> -#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBU= S_JOIN_PIPE_SELECT_MASK, pipe) >> -#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELE= CT(7) >> -#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) >> -#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS= _TRANSLATION_THROTTLE_MIN_MASK, val) >> +#define MBUS_CTL _MMIO(0x4438C) >> +#define MBUS_JOIN REG_BIT(31) >> +#define MBUS_HASHING_MODE_MASK REG_BIT(30) >> +#define MBUS_HASHING_MODE_2x2 REG_FIEL= D_PREP(MBUS_HASHING_MODE_MASK, 0) >> +#define MBUS_HASHING_MODE_1x4 REG_FIEL= D_PREP(MBUS_HASHING_MODE_MASK, 1) >> +#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK= (28, 26) >> +#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_= PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) >> +#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_P= IPE_SELECT(7) >> +#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK= (15, 13) >> +#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_P= REP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) >> +#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16= , 13) >> +#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP= (XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) > >Nitpick: I'm not sure if we're 100% consistent, but I feel like we >usually sort bitfields based on their upper bound rather than their >lower bound. So even though xe3p and pre-xe3p start at the same bit 13, >the xe3p should probably be sorted first since it ends at a higher bit >(16 vs 15). Ack. Thanks! -- Gustavo Sousa > >> =20 >> /* >> * The below are numbered starting from "S1" on gen11/gen12, but starti= ng >> @@ -51,21 +53,23 @@ >> * way things will be named by the hardware team going forward, plus it= 's more >> * consistent with how most of the rest of our registers are named. >> */ >> -#define _DBUF_CTL_S0 0x45008 >> -#define _DBUF_CTL_S1 0x44FE8 >> -#define _DBUF_CTL_S2 0x44300 >> -#define _DBUF_CTL_S3 0x44304 >> -#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ >> - _DBUF_CTL_S= 0, \ >> - _DBUF_CTL_S= 1, \ >> - _DBUF_CTL_S= 2, \ >> - _DBUF_CTL_S= 3)) >> -#define DBUF_POWER_REQUEST REG_BIT(31) >> -#define DBUF_POWER_STATE REG_BIT(30) >> -#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) >> -#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DB= UF_TRACKER_STATE_SERVICE_MASK, x) >> -#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16)= /* ADL-P+ */ >> +#define _DBUF_CTL_S0 0x45008 >> +#define _DBUF_CTL_S1 0x44FE8 >> +#define _DBUF_CTL_S2 0x44300 >> +#define _DBUF_CTL_S3 0x44304 >> +#define DBUF_CTL_S(slice) _MMIO(_PICK(sl= ice, \ >> + _DB= UF_CTL_S0, \ >> + _DB= UF_CTL_S1, \ >> + _DB= UF_CTL_S2, \ >> + _DB= UF_CTL_S3)) >> +#define DBUF_POWER_REQUEST REG_BIT(31) >> +#define DBUF_POWER_STATE REG_BIT(30) >> +#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23,= 19) >> +#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD= _PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) >> +#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK= (18, 16) /* ADL-P+ */ >> #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PRE= P(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ >> +#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20= , 16) >> +#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIEL= D_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) > >Same here. > > >Matt > >> =20 >> #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) >> #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) >>=20 >> --=20 >> 2.51.0 >>=20 > >--=20 >Matt Roper >Graphics Software Engineer >Linux GPU Platform Enablement >Intel Corporation