diff for duplicates of <1773036.BloUU6hcoj@phil> diff --git a/a/1.txt b/N1/1.txt index e17f34d..afef619 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ Hi Xing, Elaine, Am Dienstag, 2. August 2016, 21:34:12 schrieb Xing Zheng: -> From: Elaine Zhang <zhangqing@rock-chips.com> +> From: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > The goal is that we can configure the most suitable pll params > automatically. @@ -9,8 +9,8 @@ Am Dienstag, 2. August 2016, 21:34:12 schrieb Xing Zheng: > If setting freq is not supported in rockchip_pll_rate_table > rk3399_pll_rates[], we can set pll params automatically. > -> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> -> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> +> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> first off, I really like that idea of calculating the generic pll frequencies instead of duplicating these entries in every soc clock driver. diff --git a/a/content_digest b/N1/content_digest index 77dc41f..107a8e9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,25 +1,25 @@ "ref\01470144852-20708-1-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" + "ref\01470144852-20708-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org\0" + "From\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0Re: [RFC PATCH] clk: rockchip: rk3399: support pll setting automatically\0" "Date\0Mon, 29 Aug 2016 10:02:20 +0200\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - dianders@chromium.org - briannorris@chromium.org - huangtao@rock-chips.com - zhangqing@rock-chips.com - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " Elaine Zhang <zhangqing@rock-chips.com>\0" + "To\0Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" + "Cc\0huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org" + Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org + Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "Hi Xing, Elaine,\n" "\n" "Am Dienstag, 2. August 2016, 21:34:12 schrieb Xing Zheng:\n" - "> From: Elaine Zhang <zhangqing@rock-chips.com>\n" + "> From: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" "> \n" "> The goal is that we can configure the most suitable pll params\n" "> automatically.\n" @@ -27,8 +27,8 @@ "> If setting freq is not supported in rockchip_pll_rate_table\n" "> rk3399_pll_rates[], we can set pll params automatically.\n" "> \n" - "> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>\n" - "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" + "> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + "> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" "\n" "first off, I really like that idea of calculating the generic pll frequencies \n" "instead of duplicating these entries in every soc clock driver.\n" @@ -299,4 +299,4 @@ "\n" Heiko -204cfac41b3173f3c69e6149ebb1f0745970f8047eaf55bae72af4e5f4aa4ab6 +e1757cb9f4c143ee901be3d30666ea0e2a34ca1d9557a48d54ab689159a42cc9
diff --git a/a/content_digest b/N2/content_digest index 77dc41f..e40fe14 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,19 +1,8 @@ "ref\01470144852-20708-1-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" - "Subject\0Re: [RFC PATCH] clk: rockchip: rk3399: support pll setting automatically\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[RFC PATCH] clk: rockchip: rk3399: support pll setting automatically\0" "Date\0Mon, 29 Aug 2016 10:02:20 +0200\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - dianders@chromium.org - briannorris@chromium.org - huangtao@rock-chips.com - zhangqing@rock-chips.com - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " Elaine Zhang <zhangqing@rock-chips.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Xing, Elaine,\n" @@ -299,4 +288,4 @@ "\n" Heiko -204cfac41b3173f3c69e6149ebb1f0745970f8047eaf55bae72af4e5f4aa4ab6 +0dc6c4b9622e9f831d303dc9024d6683652ccb3c3220ddb651871f93ca0d1bde
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