From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Laurent Pinchart To: Jose Abreu Cc: dri-devel@lists.freedesktop.org, Fabio Estevam , Laurent Pinchart , Russell King - ARM Linux , Kieran Bingham , linux-renesas-soc@vger.kernel.org, Ulrich Hecht , Andy Yan , Vladimir Zapolskiy Subject: Re: [PATCH v2 17/29] drm: bridge: dw-hdmi: Refactor PHY power handling Date: Fri, 06 Jan 2017 16:52:15 +0200 Message-ID: <1781659.ynIBoqkrKC@avalon> In-Reply-To: References: <20161220013400.28317-1-laurent.pinchart+renesas@ideasonboard.com> <30295846.0iPnmn0IgG@avalon> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" List-ID: Hi Jose, On Friday 06 Jan 2017 10:07:03 Jose Abreu wrote: > Hi Laurent, > > Sorry for the delayed answer but I am quite busy at the moment. No worries, your help is really appreciated. > On 06-01-2017 01:48, Laurent Pinchart wrote: > > [snip] > > >>>> The TX_READY signal is documented in the i.MX6 datasheet as being a PHY > >>>> output signal, but there seems to be no HDMI TX register from which its > >>>> state can be read. Do I need to poll the HDMI_PHY_PTRPT_ENBL register > >>>> through I2C ? How long is the PHY expected to take to set TX_READY to 0 > >>>> ? > >>> > >>> TX_READY can be read from register 0x1A of phy, BIT(2) (through > >>> I2C). > >> > >> That's what I thought, I'll poll that then. Do you have any idea how long > >> it's supposed to take, to set an appropriate timeout ? > > For 3d tx phy and for 25 MHz input reference clock the power-up > time is ~1ms, there is no data in the docs to power-down time but > it should be similar. Reference clock value is board dependent > and the minimum value for HDMI shall be 13.5MHz. > > > On i.MX6 (3D TX PHY) register 0x1a reads as 0x0007 before powering down > > the PHY (by deasserting TXPWRON) and as 0x0000 immediately after. On > > RK3288 (MHL PHY) the register reads as 0x0207 and as 0x0000 immediately > > after deasserting TXPWRON. It seems that one I2C read is a sufficient > > delay for TX_READY to go low. > > > >>> Not sure if same offset for all phys though. > >> > >> Most probably not, it would be too easy :-) I'll investigate (which will > >> likely include lots of guesswork). If you can find any information about > >> that (and especially about the MHL and HDMI 2.0 PHYs) that would be very > >> appreciated, as I don't have access to any documentation that mentions a > >> TX_READY bit for those. > > > > I haven't tested the HDMI 2.0 PHY yet, but I'd be surprised if the > > TX_READY bit was in the same register at the same position. > > The info I got the register offset is from an HDMI 2.0 phy :) That's good news :-) > Notice that there are a lot of phy versions and some of them > (used in dw-hdmi) maybe customized, I don't think I have access > to that custom phys documentation. I think we will eventually have to implement PHY-specific power up and power down sequences, but for now a common sequence should work. > Please test the HDMI 2.0 phy and check if the register is the same, it > should be. I did, and it is \o/ I'll send patches. > In the meantime it would really be helpful if some of the developers > that used dw-hdmi supplied this info about the registers as they > should know exactly what phy was used. I will ask internally for the R-Car H3 SoC. -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH v2 17/29] drm: bridge: dw-hdmi: Refactor PHY power handling Date: Fri, 06 Jan 2017 16:52:15 +0200 Message-ID: <1781659.ynIBoqkrKC@avalon> References: <20161220013400.28317-1-laurent.pinchart+renesas@ideasonboard.com> <30295846.0iPnmn0IgG@avalon> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from galahad.ideasonboard.com (galahad.ideasonboard.com [IPv6:2001:4b98:dc2:45:216:3eff:febb:480d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5CFDD6EA12 for ; Fri, 6 Jan 2017 14:52:10 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jose Abreu Cc: Fabio Estevam , Laurent Pinchart , Russell King - ARM Linux , dri-devel@lists.freedesktop.org, Kieran Bingham , linux-renesas-soc@vger.kernel.org, Ulrich Hecht , Andy Yan , Vladimir Zapolskiy List-Id: dri-devel@lists.freedesktop.org SGkgSm9zZSwKCk9uIEZyaWRheSAwNiBKYW4gMjAxNyAxMDowNzowMyBKb3NlIEFicmV1IHdyb3Rl Ogo+IEhpIExhdXJlbnQsCj4gCj4gU29ycnkgZm9yIHRoZSBkZWxheWVkIGFuc3dlciBidXQgSSBh bSBxdWl0ZSBidXN5IGF0IHRoZSBtb21lbnQuCgpObyB3b3JyaWVzLCB5b3VyIGhlbHAgaXMgcmVh bGx5IGFwcHJlY2lhdGVkLgoKPiBPbiAwNi0wMS0yMDE3IDAxOjQ4LCBMYXVyZW50IFBpbmNoYXJ0 IHdyb3RlOgo+IAo+IFtzbmlwXQo+IAo+ID4+Pj4gVGhlIFRYX1JFQURZIHNpZ25hbCBpcyBkb2N1 bWVudGVkIGluIHRoZSBpLk1YNiBkYXRhc2hlZXQgYXMgYmVpbmcgYSBQSFkKPiA+Pj4+IG91dHB1 dCBzaWduYWwsIGJ1dCB0aGVyZSBzZWVtcyB0byBiZSBubyBIRE1JIFRYIHJlZ2lzdGVyIGZyb20g d2hpY2ggaXRzCj4gPj4+PiBzdGF0ZSBjYW4gYmUgcmVhZC4gRG8gSSBuZWVkIHRvIHBvbGwgdGhl IEhETUlfUEhZX1BUUlBUX0VOQkwgcmVnaXN0ZXIKPiA+Pj4+IHRocm91Z2ggSTJDID8gSG93IGxv bmcgaXMgdGhlIFBIWSBleHBlY3RlZCB0byB0YWtlIHRvIHNldCBUWF9SRUFEWSB0byAwCj4gPj4+ PiA/Cj4gPj4+IAo+ID4+PiBUWF9SRUFEWSBjYW4gYmUgcmVhZCBmcm9tIHJlZ2lzdGVyIDB4MUEg b2YgcGh5LCBCSVQoMikgKHRocm91Z2gKPiA+Pj4gSTJDKS4KPiA+PiAKPiA+PiBUaGF0J3Mgd2hh dCBJIHRob3VnaHQsIEknbGwgcG9sbCB0aGF0IHRoZW4uIERvIHlvdSBoYXZlIGFueSBpZGVhIGhv dyBsb25nCj4gPj4gaXQncyBzdXBwb3NlZCB0byB0YWtlLCB0byBzZXQgYW4gYXBwcm9wcmlhdGUg dGltZW91dCA/Cj4gCj4gRm9yIDNkIHR4IHBoeSBhbmQgZm9yIDI1IE1IeiBpbnB1dCByZWZlcmVu Y2UgY2xvY2sgdGhlIHBvd2VyLXVwCj4gdGltZSBpcyB+MW1zLCB0aGVyZSBpcyBubyBkYXRhIGlu IHRoZSBkb2NzIHRvIHBvd2VyLWRvd24gdGltZSBidXQKPiBpdCBzaG91bGQgYmUgc2ltaWxhci4g UmVmZXJlbmNlIGNsb2NrIHZhbHVlIGlzIGJvYXJkIGRlcGVuZGVudAo+IGFuZCB0aGUgbWluaW11 bSB2YWx1ZSBmb3IgSERNSSBzaGFsbCBiZSAxMy41TUh6Lgo+IAo+ID4gT24gaS5NWDYgKDNEIFRY IFBIWSkgcmVnaXN0ZXIgMHgxYSByZWFkcyBhcyAweDAwMDcgYmVmb3JlIHBvd2VyaW5nIGRvd24K PiA+IHRoZSBQSFkgKGJ5IGRlYXNzZXJ0aW5nIFRYUFdST04pIGFuZCBhcyAweDAwMDAgaW1tZWRp YXRlbHkgYWZ0ZXIuIE9uCj4gPiBSSzMyODggKE1ITCBQSFkpIHRoZSByZWdpc3RlciByZWFkcyBh cyAweDAyMDcgYW5kIGFzIDB4MDAwMCBpbW1lZGlhdGVseQo+ID4gYWZ0ZXIgZGVhc3NlcnRpbmcg VFhQV1JPTi4gSXQgc2VlbXMgdGhhdCBvbmUgSTJDIHJlYWQgaXMgYSBzdWZmaWNpZW50Cj4gPiBk ZWxheSBmb3IgVFhfUkVBRFkgdG8gZ28gbG93Lgo+ID4gCj4gPj4+IE5vdCBzdXJlIGlmIHNhbWUg b2Zmc2V0IGZvciBhbGwgcGh5cyB0aG91Z2guCj4gPj4gCj4gPj4gTW9zdCBwcm9iYWJseSBub3Qs IGl0IHdvdWxkIGJlIHRvbyBlYXN5IDotKSBJJ2xsIGludmVzdGlnYXRlICh3aGljaCB3aWxsCj4g Pj4gbGlrZWx5IGluY2x1ZGUgbG90cyBvZiBndWVzc3dvcmspLiBJZiB5b3UgY2FuIGZpbmQgYW55 IGluZm9ybWF0aW9uIGFib3V0Cj4gPj4gdGhhdCAoYW5kIGVzcGVjaWFsbHkgYWJvdXQgdGhlIE1I TCBhbmQgSERNSSAyLjAgUEhZcykgdGhhdCB3b3VsZCBiZSB2ZXJ5Cj4gPj4gYXBwcmVjaWF0ZWQs IGFzIEkgZG9uJ3QgaGF2ZSBhY2Nlc3MgdG8gYW55IGRvY3VtZW50YXRpb24gdGhhdCBtZW50aW9u cyBhCj4gPj4gVFhfUkVBRFkgYml0IGZvciB0aG9zZS4KPiA+IAo+ID4gSSBoYXZlbid0IHRlc3Rl ZCB0aGUgSERNSSAyLjAgUEhZIHlldCwgYnV0IEknZCBiZSBzdXJwcmlzZWQgaWYgdGhlCj4gPiBU WF9SRUFEWSBiaXQgd2FzIGluIHRoZSBzYW1lIHJlZ2lzdGVyIGF0IHRoZSBzYW1lIHBvc2l0aW9u Lgo+IAo+IFRoZSBpbmZvIEkgZ290IHRoZSByZWdpc3RlciBvZmZzZXQgaXMgZnJvbSBhbiBIRE1J IDIuMCBwaHkgOikKClRoYXQncyBnb29kIG5ld3MgOi0pCgo+IE5vdGljZSB0aGF0IHRoZXJlIGFy ZSBhIGxvdCBvZiBwaHkgdmVyc2lvbnMgYW5kIHNvbWUgb2YgdGhlbQo+ICh1c2VkIGluIGR3LWhk bWkpIG1heWJlIGN1c3RvbWl6ZWQsIEkgZG9uJ3QgdGhpbmsgSSBoYXZlIGFjY2Vzcwo+IHRvIHRo YXQgY3VzdG9tIHBoeXMgZG9jdW1lbnRhdGlvbi4KCkkgdGhpbmsgd2Ugd2lsbCBldmVudHVhbGx5 IGhhdmUgdG8gaW1wbGVtZW50IFBIWS1zcGVjaWZpYyBwb3dlciB1cCBhbmQgcG93ZXIgCmRvd24g c2VxdWVuY2VzLCBidXQgZm9yIG5vdyBhIGNvbW1vbiBzZXF1ZW5jZSBzaG91bGQgd29yay4KCj4g UGxlYXNlIHRlc3QgdGhlIEhETUkgMi4wIHBoeSBhbmQgY2hlY2sgaWYgdGhlIHJlZ2lzdGVyIGlz IHRoZSBzYW1lLCBpdAo+IHNob3VsZCBiZS4KCkkgZGlkLCBhbmQgaXQgaXMgXG8vIEknbGwgc2Vu ZCBwYXRjaGVzLgoKPiBJbiB0aGUgbWVhbnRpbWUgaXQgd291bGQgcmVhbGx5IGJlIGhlbHBmdWwg aWYgc29tZSBvZiB0aGUgZGV2ZWxvcGVycwo+IHRoYXQgdXNlZCBkdy1oZG1pIHN1cHBsaWVkIHRo aXMgaW5mbyBhYm91dCB0aGUgcmVnaXN0ZXJzIGFzIHRoZXkKPiBzaG91bGQga25vdyBleGFjdGx5 IHdoYXQgcGh5IHdhcyB1c2VkLgoKSSB3aWxsIGFzayBpbnRlcm5hbGx5IGZvciB0aGUgUi1DYXIg SDMgU29DLgoKLS0gClJlZ2FyZHMsCgpMYXVyZW50IFBpbmNoYXJ0CgpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRy aS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK