From: Will Deacon <will@kernel.org>
To: joro@8bytes.org, robin.murphy@arm.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jonathanh@nvidia.com,
thierry.reding@kernel.org, nicolinc@nvidia.com,
Ashish Mhetre <amhetre@nvidia.com>
Cc: catalin.marinas@arm.com, kernel-team@android.com,
Will Deacon <will@kernel.org>,
iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example
Date: Sun, 26 Jul 2026 16:00:50 +0100 [thread overview]
Message-ID: <178507371894.3389438.5885986849124953777.b4-ty@kernel.org> (raw)
In-Reply-To: <20260622065410.2780215-1-amhetre@nvidia.com>
On Mon, 22 Jun 2026 06:54:09 +0000, Ashish Mhetre wrote:
> The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
> interrupt documentation, but the binding example describes it as
> level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
> that it does not propagate the wrong trigger type.
>
>
Applied bindings update to iommu (arm/smmu/bindings), thanks!
[1/2] dt-bindings: iommu: Fix interrupt type in example
https://git.kernel.org/iommu/c/20df8037968d
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
prev parent reply other threads:[~2026-07-26 15:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 6:54 [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Ashish Mhetre
2026-06-22 6:54 ` [PATCH 2/2] arm64: tegra: Fix CMDQV interrupt type on Tegra264 Ashish Mhetre
2026-06-22 20:58 ` Nicolin Chen
2026-07-08 13:32 ` Jon Hunter
2026-06-22 16:38 ` [PATCH 1/2] dt-bindings: iommu: Fix interrupt type in example Conor Dooley
2026-06-22 20:52 ` Nicolin Chen
2026-07-08 13:32 ` Jon Hunter
2026-07-16 21:47 ` (subset) " Thierry Reding
2026-07-26 15:00 ` Will Deacon [this message]
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