From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBAFA383C86; Fri, 7 Aug 2026 16:00:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786118405; cv=none; b=loe4p+7os+DozRtFcpjiypOZcqZ6oLJVsNub9prMoqlpGcAW+tlu/pkrW1jfD+KQbmagJrLwgcPH0MGL7N6TsdCRf/LXjtoEewO7WXE4uReaZVCWkq62015j3oNtCWqIuHACi0J9CVXDs6MnEOE3gFpGhb1ImIpv7pwWsizW59k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786118405; c=relaxed/simple; bh=s1hvyLc0KKkwmP1X2/V+6E8AZejqQhMGYfb+faIrnxs=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=pYpr/i98uoER6DIJPzvmg2LIeCHKcV/ASndq4Mys467wOcELlGpQCvLx0Fh0NOq36BP1SYEgAmg2WoBPGJ3m6i92qHFylbLvwOSG/Q/L+MpXF+W/MY7hUOOTiyQ2m/t4TsYjgN4w3xvtUt8+hFlMnOV0QcZMogr4VvztDBMzxlg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=K2Ncgzw9; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yWSVYX6A; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="K2Ncgzw9"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yWSVYX6A" Date: Fri, 07 Aug 2026 15:59:59 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786118401; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c0lbATCseXkvhJK/ZqnzuOvjv10qLv5XsKD1e/QzXO4=; b=K2Ncgzw9X3uxllF9cTzf6glCGl4hxNq3IBtjCq4MXhaVRSJNLXZBKXOay1JTIlPAzs4E3P b7oQ0beB8YY76GgKRW14qcXuQQnH4Y24chxo0MwOF6AWo2TMlKAP+QzZ6Us2/Y4/IKOZj3 2FV0Zxbx2EZgbdSeXHqTCzVft8iWw6ZhYVqfEy1c6nhc640RHAZDENrO4rmZ8iJy/MQHBU Bu5r9dbGBGHyFAdOxjbFPBA/W7Wr2y2AK6b99qgeZFjSvUgHU4LoHqxYJHhPblqRigGdMb l/tto7w2iNZ9pmT8oA8ObPxNzYSESl4AQ6PE/fqTz/rdoZv3LexYs4beQZU+wQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786118401; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c0lbATCseXkvhJK/ZqnzuOvjv10qLv5XsKD1e/QzXO4=; b=yWSVYX6A6t1aeABnDd1XD81WhoJDzU+px3AxCn7F8e5Aw7Kh630CSbvsGQWUi03lXwM23Q uWnwbA0uKE91XfBA== From: "tip-bot2 for Dmitry Ilvokhin" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] x86/paravirt: Trace contended_release on unlock Cc: Peter Zijlstra , Dmitry Ilvokhin , Juergen Gross , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <17fa67f9fa4cf93f1150725e89f5f916e41a9b6f.1785778551.git.d@ilvokhin.com> References: <17fa67f9fa4cf93f1150725e89f5f916e41a9b6f.1785778551.git.d@ilvokhin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178611839980.708.13617653015052531574.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: 087116fefbf343ce63b8911cf494e059e9679432 Gitweb: https://git.kernel.org/tip/087116fefbf343ce63b8911cf494e059e96= 79432 Author: Dmitry Ilvokhin AuthorDate: Tue, 04 Aug 2026 07:15:45=20 Committer: Peter Zijlstra CommitterDate: Fri, 07 Aug 2026 17:58:10 +02:00 x86/paravirt: Trace contended_release on unlock On PARAVIRT_SPINLOCKS=3Dy kernels queued_spin_unlock() is dispatched through a static_call(). Those PARAVIRT_SPINLOCKS=3Dy kernels are quite popular. Gating contended_release behind a static branch would leave a NOP on the unlock hot path even, when the tracepoint is disabled. Since the static_call() is already present, swap its target to a traced unlock, when the tracepoint is enabled instead. When contended_release tracepoint is disabled the target is the plain unlock (an inline store on native x86_64), so the unlock path is unchanged and the tracepoint is truly zero-cost. Provide two traced variants, native_queued_spin_unlock_traced() and pv_queued_spin_unlock_traced(), so each tail-calls its own base unlock directly rather than recursing through the now-traced static_call(). Teach pv_is_native_spin_unlock() that the traced native variant still counts as native. Only PARAVIRT_SPINLOCKS=3Dy is affected. PARAVIRT_SPINLOCKS=3Dn keeps the generic static-branch path. Suggested-by: Peter Zijlstra Signed-off-by: Dmitry Ilvokhin Signed-off-by: Peter Zijlstra (Intel) Acked-by: Juergen Gross Link: https://patch.msgid.link/17fa67f9fa4cf93f1150725e89f5f916e41a9b6f.17857= 78551.git.d@ilvokhin.com --- arch/x86/include/asm/paravirt-spinlock.h | 2 +- arch/x86/kernel/paravirt-spinlocks.c | 53 ++++++++++++++++++++++- 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/paravirt-spinlock.h b/arch/x86/include/asm/= paravirt-spinlock.h index ff73583..302bc2b 100644 --- a/arch/x86/include/asm/paravirt-spinlock.h +++ b/arch/x86/include/asm/paravirt-spinlock.h @@ -99,6 +99,8 @@ bool __raw_callee_save___native_vcpu_is_preempted(long cpu); =20 void __init native_pv_lock_init(void); __visible void __native_queued_spin_unlock(struct qspinlock *lock); +__visible void native_queued_spin_unlock_traced(struct qspinlock *lock); +__visible void pv_queued_spin_unlock_traced(struct qspinlock *lock); bool pv_is_native_spin_unlock(void); __visible bool __native_vcpu_is_preempted(long cpu); bool pv_is_native_vcpu_is_preempted(void); diff --git a/arch/x86/kernel/paravirt-spinlocks.c b/arch/x86/kernel/paravirt-= spinlocks.c index ddc19dc..ca12b36 100644 --- a/arch/x86/kernel/paravirt-spinlocks.c +++ b/arch/x86/kernel/paravirt-spinlocks.c @@ -7,6 +7,7 @@ #include #include #include +#include =20 DEFINE_STATIC_KEY_FALSE(virt_spin_lock_key); =20 @@ -30,10 +31,58 @@ EXPORT_STATIC_CALL_TRAMP(queued_spin_lock_slowpath); DEFINE_STATIC_CALL(queued_spin_unlock, __raw_callee_save___native_queued_spi= n_unlock); EXPORT_STATIC_CALL_TRAMP(queued_spin_unlock); =20 +/* + * Traced unlock variants, swapped in via static_call while the + * contended_release tracepoint is enabled. Two of them, so each tail calls = its + * own base directly. + */ +__visible void native_queued_spin_unlock_traced(struct qspinlock *lock) +{ + if (queued_spin_is_contended(lock)) + trace_call__contended_release(lock); + native_queued_spin_unlock(lock); +} +PV_CALLEE_SAVE_REGS_THUNK(native_queued_spin_unlock_traced); + +__visible void pv_queued_spin_unlock_traced(struct qspinlock *lock) +{ + if (queued_spin_is_contended(lock)) + trace_call__contended_release(lock); + __raw_callee_save___pv_queued_spin_unlock(lock); +} +PV_CALLEE_SAVE_REGS_THUNK(pv_queued_spin_unlock_traced); + bool pv_is_native_spin_unlock(void) { - return static_call_query(queued_spin_unlock) =3D=3D - __raw_callee_save___native_queued_spin_unlock; + void *unlock =3D static_call_query(queued_spin_unlock); + + return unlock =3D=3D __raw_callee_save___native_queued_spin_unlock || + unlock =3D=3D __raw_callee_save_native_queued_spin_unlock_traced; +} + +int arch_contended_release_trace_reg(void) +{ + void *cur =3D static_call_query(queued_spin_unlock); + + if (cur =3D=3D __raw_callee_save___native_queued_spin_unlock) + static_call_update(queued_spin_unlock, + __raw_callee_save_native_queued_spin_unlock_traced); + else if (cur =3D=3D __raw_callee_save___pv_queued_spin_unlock) + static_call_update(queued_spin_unlock, + __raw_callee_save_pv_queued_spin_unlock_traced); + return 0; +} + +void arch_contended_release_trace_unreg(void) +{ + void *cur =3D static_call_query(queued_spin_unlock); + + if (cur =3D=3D __raw_callee_save_native_queued_spin_unlock_traced) + static_call_update(queued_spin_unlock, + __raw_callee_save___native_queued_spin_unlock); + else if (cur =3D=3D __raw_callee_save_pv_queued_spin_unlock_traced) + static_call_update(queued_spin_unlock, + __raw_callee_save___pv_queued_spin_unlock); } =20 __visible bool __native_vcpu_is_preempted(long cpu)