diff for duplicates of <1788169.FUQDsLAmXg@wasted.cogentembedded.com> diff --git a/a/1.txt b/N1/1.txt index 5385730..0d545e9 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -55,7 +55,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + #address-cells = <1>; + #size-cells = <0>; + -+ cpu0: cpu@0 { ++ cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; @@ -65,7 +65,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + next-level-cache = <&L2_CA15>; + }; + -+ cpu1: cpu@1 { ++ cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; @@ -74,7 +74,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + next-level-cache = <&L2_CA15>; + }; + -+ L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + cache-unified; @@ -91,7 +91,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + #size-cells = <2>; + ranges; + -+ gic: interrupt-controller@f1001000 { ++ gic: interrupt-controller at f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; @@ -115,14 +115,14 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + IRQ_TYPE_LEVEL_LOW)>; + }; + -+ sysc: system-controller@e6180000 { ++ sysc: system-controller at e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ -+ cpg_clocks: cpg_clocks@e6150000 { ++ cpg_clocks: cpg_clocks at e6150000 { + compatible = "renesas,r8a7792-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; @@ -157,7 +157,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + }; + + /* Gate clocks */ -+ mstp2_clks: mstp2_clks@e6150138 { ++ mstp2_clks: mstp2_clks at e6150138 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; @@ -168,7 +168,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + >; + clock-output-names = "sys-dmac1", "sys-dmac0"; + }; -+ mstp4_clks: mstp4_clks@e6150140 { ++ mstp4_clks: mstp4_clks at e6150140 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; @@ -177,7 +177,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + clock-indices = <R8A7792_CLK_IRQC>; + clock-output-names = "irqc"; + }; -+ mstp7_clks: mstp7_clks@e615014c { ++ mstp7_clks: mstp7_clks at e615014c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/a/content_digest b/N1/content_digest index 24fee0f..2d9050f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,8 @@ "ref\012536856.AsKMEpuejQ@wasted.cogentembedded.com\0" - "From\0Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\0" + "From\0sergei.shtylyov@cogentembedded.com (Sergei Shtylyov)\0" "Subject\0[PATCH v3 06/12] ARM: dts: r8a7792: initial SoC device tree\0" "Date\0Thu, 09 Jun 2016 00:17:59 +0300\0" - "To\0horms@verge.net.au" - linux-renesas-soc@vger.kernel.org - robh+dt@kernel.org - pawel.moll@arm.com - mark.rutland@arm.com - ijc+devicetree@hellion.org.uk - galak@codeaurora.org - " devicetree@vger.kernel.org\0" - "Cc\0magnus.damm@gmail.com" - linux@arm.linux.org.uk - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,\n" @@ -72,7 +62,7 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu0: cpu@0 {\n" + "+\t\tcpu0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a15\";\n" "+\t\t\treg = <0>;\n" @@ -82,7 +72,7 @@ "+\t\t\tnext-level-cache = <&L2_CA15>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu1: cpu@1 {\n" + "+\t\tcpu1: cpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a15\";\n" "+\t\t\treg = <1>;\n" @@ -91,7 +81,7 @@ "+\t\t\tnext-level-cache = <&L2_CA15>;\n" "+\t\t};\n" "+\n" - "+\t\tL2_CA15: cache-controller@0 {\n" + "+\t\tL2_CA15: cache-controller at 0 {\n" "+\t\t\tcompatible = \"cache\";\n" "+\t\t\treg = <0>;\n" "+\t\t\tcache-unified;\n" @@ -108,7 +98,7 @@ "+\t\t#size-cells = <2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tgic: interrupt-controller@f1001000 {\n" + "+\t\tgic: interrupt-controller at f1001000 {\n" "+\t\t\tcompatible = \"arm,gic-400\";\n" "+\t\t\t#interrupt-cells = <3>;\n" "+\t\t\tinterrupt-controller;\n" @@ -132,14 +122,14 @@ "+\t\t\t\t IRQ_TYPE_LEVEL_LOW)>;\n" "+\t\t};\n" "+\n" - "+\t\tsysc: system-controller@e6180000 {\n" + "+\t\tsysc: system-controller at e6180000 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-sysc\";\n" "+\t\t\treg = <0 0xe6180000 0 0x0200>;\n" "+\t\t\t#power-domain-cells = <1>;\n" "+\t\t};\n" "+\n" "+\t\t/* Special CPG clocks */\n" - "+\t\tcpg_clocks: cpg_clocks@e6150000 {\n" + "+\t\tcpg_clocks: cpg_clocks at e6150000 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-cpg-clocks\",\n" "+\t\t\t\t \"renesas,rcar-gen2-cpg-clocks\";\n" "+\t\t\treg = <0 0xe6150000 0 0x1000>;\n" @@ -174,7 +164,7 @@ "+\t\t};\n" "+\n" "+\t\t/* Gate clocks */\n" - "+\t\tmstp2_clks: mstp2_clks@e6150138 {\n" + "+\t\tmstp2_clks: mstp2_clks at e6150138 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;\n" @@ -185,7 +175,7 @@ "+\t\t\t>;\n" "+\t\t\tclock-output-names = \"sys-dmac1\", \"sys-dmac0\";\n" "+\t\t};\n" - "+\t\tmstp4_clks: mstp4_clks@e6150140 {\n" + "+\t\tmstp4_clks: mstp4_clks at e6150140 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;\n" @@ -194,7 +184,7 @@ "+\t\t\tclock-indices = <R8A7792_CLK_IRQC>;\n" "+\t\t\tclock-output-names = \"irqc\";\n" "+\t\t};\n" - "+\t\tmstp7_clks: mstp7_clks@e615014c {\n" + "+\t\tmstp7_clks: mstp7_clks at e615014c {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;\n" @@ -229,4 +219,4 @@ "+\t};\n" +}; -5647610def5949fb328924acc00b134d9ca47ebfcb8b1d759d8109e8a0048604 +f9deee7641c29fb4cb4b947987eb4fb9688a72b43e242e18291e419816bffba8
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