diff for duplicates of <1788707.rfxhNfegGu@phil> diff --git a/a/1.txt b/N1/1.txt index 7608aaf..3a0cee0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -6,7 +6,7 @@ Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: > This patch add basic support for it with DMAC / UART / CRU / pinctrl > enabled. > -> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> +> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > --- > > arch/arm/boot/dts/rk1108.dtsi | 420 @@ -279,3 +279,7 @@ through different branches. Thanks Heiko +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 00928ab..9837222 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,20 @@ "ref\01478175975-11779-1-git-send-email-andy.yan@rock-chips.com\0" "ref\01478176848-12132-1-git-send-email-andy.yan@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" + "ref\01478176848-12132-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org\0" + "From\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC\0" "Date\0Fri, 04 Nov 2016 09:00:05 +0100\0" - "To\0Andy Yan <andy.yan@rock-chips.com>\0" - "Cc\0elaine.zhang@rock-chips.com" - mturquette@baylibre.com - linux-rockchip@lists.infradead.org - devicetree@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - linux@armlinux.org.uk - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" + "Cc\0elaine.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org" + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan:\n" @@ -24,7 +25,7 @@ "> This patch add basic support for it with DMAC / UART / CRU / pinctrl\n" "> enabled.\n" "> \n" - "> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>\n" + "> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" "> ---\n" "> \n" "> arch/arm/boot/dts/rk1108.dtsi | 420\n" @@ -296,6 +297,10 @@ "\n" "\n" "Thanks\n" - Heiko + "Heiko\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -0925a98b63a170e9b0a46109e66cb17dcfb3a51e6088e6ca182253a0c6c552a4 +acca14244f8c276b1b453f3dbce22298bf2449c350ca6f56dcce673845b54ab1
diff --git a/a/1.txt b/N2/1.txt index 7608aaf..bb9f890 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -84,7 +84,7 @@ Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu0: cpu@f00 { +> + cpu0: cpu at f00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf00>; @@ -101,7 +101,7 @@ unnecessary empty line > + #size-cells = <1>; > + ranges; > + -> + pdma: pdma@102a0000 { +> + pdma: pdma at 102a0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x102a0000 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -137,7 +137,7 @@ CPU_MASK_SIMPLE(4)? You only have one core, not 4. > + #clock-cells = <0>; > + }; > + -> + bus_intmem@10080000 { +> + bus_intmem at 10080000 { > + compatible = "mmio-sram"; > + reg = <0x10080000 0x2000>; > + #address-cells = <1>; @@ -145,12 +145,12 @@ CPU_MASK_SIMPLE(4)? You only have one core, not 4. > + ranges = <0 0x10080000 0x2000>; > + }; > + -> + grf: syscon@10300000 { +> + grf: syscon at 10300000 { > + compatible = "rockchip,rk1108-grf", "syscon"; > + reg = <0x10300000 0x1000>; > + }; > + -> + emmc: dwmmc@30110000 { +> + emmc: dwmmc at 30110000 { > + compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; > + clock-freq-min-max = <400000 150000000>; > + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, @@ -162,7 +162,7 @@ CPU_MASK_SIMPLE(4)? You only have one core, not 4. > + status = "disabled"; > + }; > + -> + sdio: dwmmc@30120000 { +> + sdio: dwmmc at 30120000 { > + compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; > + clock-freq-min-max = <400000 150000000>; > + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, @@ -174,7 +174,7 @@ CPU_MASK_SIMPLE(4)? You only have one core, not 4. > + status = "disabled"; > + }; > + -> + sdmmc: dwmmc@30130000 { +> + sdmmc: dwmmc at 30130000 { ordering by register address please (uart2 before sdmmc etc; same for everything else) @@ -191,7 +191,7 @@ everything else) > + status = "disabled"; > + }; > + -> + uart2: serial@10210000 { +> + uart2: serial at 10210000 { > + compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; > + reg = <0x10210000 0x100>; > + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -205,7 +205,7 @@ everything else) > + status = "disabled"; > + }; > + -> + uart1: serial@10220000 { +> + uart1: serial at 10220000 { > + compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; > + reg = <0x10220000 0x100>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -219,7 +219,7 @@ everything else) > + status = "disabled"; > + }; > + -> + uart0: serial@10230000 { +> + uart0: serial at 10230000 { > + compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; > + reg = <0x10230000 0x100>; > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -233,7 +233,7 @@ everything else) > + status = "disabled"; > + }; > + -> + cru: clock-controller@20200000 { +> + cru: clock-controller at 20200000 { > + compatible = "rockchip,rk1108-cru"; > + reg = <0x20200000 0x1000>; > + rockchip,grf = <&grf>; @@ -241,7 +241,7 @@ everything else) > + #reset-cells = <1>; > + }; > + -> + gic: interrupt-controller@32010000 { +> + gic: interrupt-controller at 32010000 { > + compatible = "arm,cortex-a15-gic"; compatible = "arm,gic-400"; ? diff --git a/a/content_digest b/N2/content_digest index 00928ab..60a12bd 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,19 +1,9 @@ "ref\01478175975-11779-1-git-send-email-andy.yan@rock-chips.com\0" "ref\01478176848-12132-1-git-send-email-andy.yan@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC\0" "Date\0Fri, 04 Nov 2016 09:00:05 +0100\0" - "To\0Andy Yan <andy.yan@rock-chips.com>\0" - "Cc\0elaine.zhang@rock-chips.com" - mturquette@baylibre.com - linux-rockchip@lists.infradead.org - devicetree@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - linux@armlinux.org.uk - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Am Donnerstag, 3. November 2016, 20:40:48 CET schrieb Andy Yan:\n" @@ -102,7 +92,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu0: cpu@f00 {\n" + "> +\t\tcpu0: cpu at f00 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf00>;\n" @@ -119,7 +109,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tpdma: pdma@102a0000 {\n" + "> +\t\tpdma: pdma at 102a0000 {\n" "> +\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" "> +\t\t\treg = <0x102a0000 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -155,7 +145,7 @@ "> +\t\t#clock-cells = <0>;\n" "> +\t};\n" "> +\n" - "> +\tbus_intmem@10080000 {\n" + "> +\tbus_intmem at 10080000 {\n" "> +\t\tcompatible = \"mmio-sram\";\n" "> +\t\treg = <0x10080000 0x2000>;\n" "> +\t\t#address-cells = <1>;\n" @@ -163,12 +153,12 @@ "> +\t\tranges = <0 0x10080000 0x2000>;\n" "> +\t};\n" "> +\n" - "> +\tgrf: syscon@10300000 {\n" + "> +\tgrf: syscon at 10300000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-grf\", \"syscon\";\n" "> +\t\treg = <0x10300000 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\temmc: dwmmc@30110000 {\n" + "> +\temmc: dwmmc at 30110000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "> +\t\tclock-freq-min-max = <400000 150000000>;\n" "> +\t\tclocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,\n" @@ -180,7 +170,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tsdio: dwmmc@30120000 {\n" + "> +\tsdio: dwmmc at 30120000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n" "> +\t\tclock-freq-min-max = <400000 150000000>;\n" "> +\t\tclocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,\n" @@ -192,7 +182,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tsdmmc: dwmmc@30130000 {\n" + "> +\tsdmmc: dwmmc at 30130000 {\n" "\n" "ordering by register address please (uart2 before sdmmc etc; same for \n" "everything else)\n" @@ -209,7 +199,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tuart2: serial@10210000 {\n" + "> +\tuart2: serial at 10210000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x10210000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -223,7 +213,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tuart1: serial@10220000 {\n" + "> +\tuart1: serial at 10220000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x10220000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -237,7 +227,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tuart0: serial@10230000 {\n" + "> +\tuart0: serial at 10230000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x10230000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -251,7 +241,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tcru: clock-controller@20200000 {\n" + "> +\tcru: clock-controller at 20200000 {\n" "> +\t\tcompatible = \"rockchip,rk1108-cru\";\n" "> +\t\treg = <0x20200000 0x1000>;\n" "> +\t\trockchip,grf = <&grf>;\n" @@ -259,7 +249,7 @@ "> +\t\t#reset-cells = <1>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@32010000 {\n" + "> +\tgic: interrupt-controller at 32010000 {\n" "> +\t\tcompatible = \"arm,cortex-a15-gic\";\n" "\n" "compatible = \"arm,gic-400\"; ?\n" @@ -298,4 +288,4 @@ "Thanks\n" Heiko -0925a98b63a170e9b0a46109e66cb17dcfb3a51e6088e6ca182253a0c6c552a4 +0a33db9dd377dbb4eff55030616afcdf56c46e05a01525495ebeaccad6b48fb5
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