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charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg bW9yZSBzZXZlcmUKaXNzdWUocykgaW4gb3RoZXIgcGF0Y2hlcyBvZiB0aGlzIHNlcmllcy4gVGhp cyBtYWlsIGlzIG9ubHkgYW4gRllJLCBpbiBjYXNlCnlvdSB3YW50IHRvIGFkZHJlc3MgdGhlIG5p dCBwaWNrcyBiZWxvdyB3aGVuIHlvdSByZXNwaW4uCgpMb3cgcHJpb3JpdHkgLyBuaXQgcGlja3Mg Zm9yIHlvdXIgY29uc2lkZXJhdGlvbjoKCi0gW0xvd10gVGhlIG5ldyBiaW5kaW5nCiAgRG9jdW1l bnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL25ldC9wY3Mvcm9ja2NoaXAscmszNTY4LXhwY3Mu eWFtbOKApgoKLS0KCmR0LWJpbmRpbmdzOiBuZXQ6IHBjczogYWRkIHJvY2tjaGlwLHJrMzU2OC14 cGNzIHN1cHBvcnQKClRoaXMgcGF0Y2ggYWRkcyBhIGRldmljZSB0cmVlIGJpbmRpbmcgZm9yIHRo ZSBTeW5vcHN5cyBEZXNpZ25XYXJlIFhQQ1Mgb24KdGhlIFJvY2tjaGlwIFJLMzU2OCBTb0MuIFRo ZSBYUENTIHNpdHMgb24gdGhlIEFQQjMgYnVzIGFuZCBjb25uZWN0cwppbnRlcm5hbGx5IHRvIHRo ZSBOYW5lbmcgQ29tYm8gU2VyRGVzIFBIWS4gSXQgc3VwcG9ydHMgMTAwMEJBU0UtWCwgU0dNSUkK YW5kIFFTR01JSS4KCj4gZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5k aW5ncy9uZXQvcGNzL3JvY2tjaGlwLHJrMzU2OC14cGNzLnlhbWwgYi9Eb2N1bWVudGF0aW9uL2Rl dmljZXRyZWUvYmluZGluZ3MvbmV0L3Bjcy9yb2NrY2hpcCxyazM1NjgteHBjcy55YW1sCj4gbmV3 IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi5hMzMxODgwZWIxMWMxCj4g LS0tIC9kZXYvbnVsbAo+ICsrKyBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9u ZXQvcGNzL3JvY2tjaGlwLHJrMzU2OC14cGNzLnlhbWwKClsgLi4uIF0KCj4gK3Byb3BlcnRpZXM6 Cj4gKyAgY29tcGF0aWJsZToKPiArICAgIGNvbnN0OiByb2NrY2hpcCxyazM1NjgteHBjcwo+ICsK PiArICByZWc6Cj4gKyAgICBtYXhJdGVtczogMQo+ICsKPiArICBjbG9ja3M6Cj4gKyAgICBpdGVt czoKPiArICAgICAgLSBkZXNjcmlwdGlvbjogQVBCMyBidXMgaW50ZXJmYWNlIGNsb2NrIChjbGtf Y3NyX2kpLCByZXF1aXJlZCBmb3IgcmVnaXN0ZXIgYWNjZXNzCj4gKyAgICAgIC0gZGVzY3JpcHRp b246IEVFRSBjbG9jayAoY2xrX2VlZV9pKSwgcmVxdWlyZWQgZm9yIEVuZXJneSBFZmZpY2llbnQg RXRoZXJuZXQgb3BlcmF0aW9uCj4gKwo+ICsgIGNsb2NrLW5hbWVzOgo+ICsgICAgaXRlbXM6Cj4g KyAgICAgIC0gY29uc3Q6IGNzcgo+ICsgICAgICAtIGNvbnN0OiBlZWUKPiArCj4gKyAgcGh5czoK PiArICAgIG1heEl0ZW1zOiAxCj4gKwo+ICsgIHBvd2VyLWRvbWFpbnM6Cj4gKyAgICBtYXhJdGVt czogMQo+ICsKPiArcmVxdWlyZWQ6Cj4gKyAgLSBjb21wYXRpYmxlCj4gKyAgLSByZWcKPiArICAt IGNsb2Nrcwo+ICsgIC0gY2xvY2stbmFtZXMKPiArICAtIHBoeXMKPiArICAtIHBvd2VyLWRvbWFp bnMKPiArCj4gK2FkZGl0aW9uYWxQcm9wZXJ0aWVzOiBmYWxzZQoKW1NldmVyaXR5OiBMb3ddClNo b3VsZCB0aGlzIGJpbmRpbmcgbGV0IHRoZSBYUENTIGFjdCBhcyBhIGNsb2NrIHByb3ZpZGVyPwoK VGhlIFJLMzU2OCBDUlUgdXNlcyBYUENTLW5hbWVkIGNsb2NrcyBhcyBwYXJlbnRzIGZvciB0aGUg R01BQyBSWC9UWAptdXhlcywgaW4gZHJpdmVycy9jbGsvcm9ja2NoaXAvY2xrLXJrMzU2OC5jOgoK UE5BTUUobXV4X2dtYWMwX3J4X3R4X3ApID0geyAiY2xrX2dtYWMwX3JnbWlpX3NwZWVkIiwgImNs a19nbWFjMF9ybWlpX3NwZWVkIiwgImNsa19nbWFjMF94cGNzX21paSIgfTsKUE5BTUUobXV4X2dt YWMxX3J4X3R4X3ApID0geyAiY2xrX2dtYWMxX3JnbWlpX3NwZWVkIiwgImNsa19nbWFjMV9ybWlp X3NwZWVkIiwgImNsa19nbWFjMV94cGNzX21paSIgfTsKClRoZXNlIGFyZSB0aGUgcGFyZW50cyBv ZiBTQ0xLX0dNQUMwX1JYX1RYIGFuZCBTQ0xLX0dNQUMxX1JYX1RYLgpyazM1NngtYmFzZS5kdHNp IHBhc3NlcyB0aG9zZSBjbG9ja3MgdG8gdGhlIEdNQUMgYXMgbWFjX2Nsa19yeCwKbWFjX2Nsa190 eCBhbmQgY2xrX21hY19zcGVlZC4gTm90aGluZyBpbiB0aGUgdHJlZSByZWdpc3RlcnMKY2xrX2dt YWMwX3hwY3NfbWlpIG9yIGNsa19nbWFjMV94cGNzX21paSB0b2RheS4KCkZvciBTR01JSSBvbiBH TUFDMC9HTUFDMSwgYSBib2FyZCBEVCB3b3VsZCBuZWVkIGFzc2lnbmVkLWNsb2NrLXBhcmVudHMK dG8gcG9pbnQgU0NMS19HTUFDbl9SWF9UWCBhdCB0aGUgWFBDUyBNSUkgY2xvY2suIFRoaXMgc2No ZW1hIGhhcyBubwojY2xvY2stY2VsbHMgb3IgY2xvY2stb3V0cHV0LW5hbWVzLCBhbmQgYWRkaXRp b25hbFByb3BlcnRpZXM6IGZhbHNlCm1lYW5zIGR0X2JpbmRpbmdfY2hlY2sgcmVqZWN0cyB0aGVt LiBTbyB0aGUgRFQgY2FuJ3QgbmFtZSB0aGUgWFBDUyBub2RlCmFzIHRoZSBzb3VyY2Ugb2YgdGhh dCBjbG9jay4gQm9hcmRzIHdvdWxkIGhhdmUgdG8gdXNlIGEgZml4ZWQtY2xvY2sKcGxhY2Vob2xk ZXIgY2FycnlpbmcgdGhlIENSVSdzIHN0cmluZyBuYW1lIGluc3RlYWQuCgpEb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3Mvd3JpdGluZy1iaW5kaW5ncy5yc3Qgc2F5cyAiRE8gYXR0ZW1w dAp0byBtYWtlIGJpbmRpbmdzIGNvbXBsZXRlIGV2ZW4gaWYgYSBkcml2ZXIgZG9lc24ndCBzdXBw b3J0IHNvbWUKZmVhdHVyZXMiLiBUaGUgY29tbWl0IG1lc3NhZ2UgZXhwbGFpbnMgd2h5IHRoZSBT UlNUX1hQQ1MqIHJlc2V0cyBhcmUKbGVmdCBvdXQgYnV0IHNheXMgbm90aGluZyBhYm91dCB0aGUg TUlJIGNsb2NrIG91dHB1dHMuCgpDb3VsZCAjY2xvY2stY2VsbHMgKGFuZCBjbG9jay1vdXRwdXQt bmFtZXMsIGlmIG5lZWRlZCkgYmUgYWRkZWQgZm9yIHRoZQpwZXItcG9ydCBNSUkgY2xvY2tzPyBP ciBjb3VsZCB0aGUgY29tbWl0IG1lc3NhZ2Ugc2F5IHdoeSB0aGV5IGFyZSBsZWZ0Cm91dD8KCj4g Kwo+ICtleGFtcGxlczoKClsgLi4uIF0KCi0tIApTYXNoaWtvIEFJIHJldmlldyDCtyBodHRwczov L25ldGRldi1haS5ib3RzLmxpbnV4LmRldi9zYXNoaWtvLyMvcGF0Y2hzZXQvMjAyNjEwMTcwNTQ0 MDYuMTgyODA2MS0xLWNvaWFwcmFudCU0MGdtYWlsLmNvbQoKX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KTGludXgtcm9ja2NoaXAgbWFpbGluZyBsaXN0Ckxp bnV4LXJvY2tjaGlwQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5v cmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yb2NrY2hpcAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A71093FF8B6; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zogmw17u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 320A71F000C5; Sun, 18 Oct 2026 06:45:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792305930; bh=7foX2sltJUBrduQaVLWCnWkINXoCkL4ewEk5y5ZKQ58=; h=Subject:From:To:Cc:Date:In-Reply-To:References; b=Zogmw17uoSjVmvTpbTjGgSQHk/XQKQObiSDRXGOMLOqj8YxLEaWE4DCQwudfUyuzJ GEjLPRfApfAvyS6x9APx5Yr4MO9E5I5b3tCAZ13Dkxzy9mbt+Ekz4FsLZNlY/nKd2U HGStFM2SUZoqs2sWqHojVeCh/dswU9yY6cQkSWRrSmQYR3pZbp9SFVeSCJajUEv3SJ iWzKzWf9ZXpjSsIVp9Pj4sxX2VktaHgX/3fcJ3GC+2rWUAisjlXlQsKYqmQsJ5SeS/ quS33+0yUAwrG7STT+Sqeo/LJ9sCsyXWivR63BWr+mj2518y1r7+JfT+BwB3K1Qirz tOmqHQkZZMKWQ== Subject: Re: [PATCH net-next v12 2/6] dt-bindings: net: pcs: add rockchip,rk3568-xpcs support From: netdev-bot+sashiko@kernel.org To: coiaprant@gmail.com Cc: kuba@kernel.org, netdev@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, maxime.chevallier@bootlin.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, hkallweit1@gmail.com, linux@armlinux.org.uk, david.wu@rock-chips.com, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Sun, 18 Oct 2026 06:45:28 +0000 Message-ID: <179230592878.3135.12873232337699291552@kernel.org> In-Reply-To: <20261017054406.1828061-3-coiaprant@gmail.com> References: <20261017054406.1828061-3-coiaprant@gmail.com> X-sashiko-severity: Low Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Thank you for your contribution! Sashiko AI review found more severe issue(s) in other patches of this series. This mail is only an FYI, in case you want to address the nit picks below when you respin. Low priority / nit picks for your consideration: - [Low] The new binding Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml… -- dt-bindings: net: pcs: add rockchip,rk3568-xpcs support This patch adds a device tree binding for the Synopsys DesignWare XPCS on the Rockchip RK3568 SoC. The XPCS sits on the APB3 bus and connects internally to the Naneng Combo SerDes PHY. It supports 1000BASE-X, SGMII and QSGMII. > diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml > new file mode 100644 > index 0000000000000..a331880eb11c1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml [ ... ] > +properties: > + compatible: > + const: rockchip,rk3568-xpcs > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: APB3 bus interface clock (clk_csr_i), required for register access > + - description: EEE clock (clk_eee_i), required for Energy Efficient Ethernet operation > + > + clock-names: > + items: > + - const: csr > + - const: eee > + > + phys: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - phys > + - power-domains > + > +additionalProperties: false [Severity: Low] Should this binding let the XPCS act as a clock provider? The RK3568 CRU uses XPCS-named clocks as parents for the GMAC RX/TX muxes, in drivers/clk/rockchip/clk-rk3568.c: PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; These are the parents of SCLK_GMAC0_RX_TX and SCLK_GMAC1_RX_TX. rk356x-base.dtsi passes those clocks to the GMAC as mac_clk_rx, mac_clk_tx and clk_mac_speed. Nothing in the tree registers clk_gmac0_xpcs_mii or clk_gmac1_xpcs_mii today. For SGMII on GMAC0/GMAC1, a board DT would need assigned-clock-parents to point SCLK_GMACn_RX_TX at the XPCS MII clock. This schema has no #clock-cells or clock-output-names, and additionalProperties: false means dt_binding_check rejects them. So the DT can't name the XPCS node as the source of that clock. Boards would have to use a fixed-clock placeholder carrying the CRU's string name instead. Documentation/devicetree/bindings/writing-bindings.rst says "DO attempt to make bindings complete even if a driver doesn't support some features". The commit message explains why the SRST_XPCS* resets are left out but says nothing about the MII clock outputs. Could #clock-cells (and clock-output-names, if needed) be added for the per-port MII clocks? Or could the commit message say why they are left out? > + > +examples: [ ... ] -- Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261017054406.1828061-1-coiaprant%40gmail.com