Re: [PATCH net 0/2] ice: dpll: fix updates of the SyncE CGU registers on E825

[patchwork-bot+netdevbpf@kernel.org]

Hello:

This series was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Tue, 10 Nov 2026 10:43:48 +0100 you wrote:
> All E825C PFs share the CGU registers R10 and R11, which hold the mux and
> the divider of the two recovered clock outputs. Both patches fix how a link
> change updates them, both found in review:
> 
> - Patch 1 adds a lock shared by all PFs around the read-modify-write
>   sequences of these registers. A link change on one PF could undo an RCLK
>   pin change made by another PF.
> - Patch 2 lets a link change set the divider of an output only when its
>   port drives that output. Every port set it from its own link speed,
>   which is wrong when ports run at different speeds.
> 
> [...]

Here is the summary with links:
  - [net,1/2] ice: dpll: serialize changes of the SyncE CGU registers
    https://git.kernel.org/netdev/net/c/0afbc079d87e
  - [net,2/2] ice: dpll: set the SyncE divider only for the port driving the output
    https://git.kernel.org/netdev/net/c/164721e16b82

You are awesome, thank you!
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