Re: [PATCH v3] PCI: Reserve prefetchable window headroom for Resizable BARs

[James R Taylor <jrtaylor11@gmail.com>]

Hi Geramy,

On Sat, Aug 29, 2026, Geramy Loveless wrote:
> Firmware typically sizes prefetchable bridge windows for the boot-time
> BAR size. Behind a fixed (non-hotplug) PCIe switch fabric, there is then
> no room for a driver to grow a Resizable BAR afterwards

I've been running v3 since 27 October on a different kind of fabric from
yours, a USB4/Thunderbolt eGPU, and it gives the GPU its full BAR there
too. In case the data point is useful:

  Host:  Minisforum UM890 Pro (AMD Ryzen 9 8945HS, Hawk Point),
         BIOS 1.06
  Dock:  Minisforum DEG2 (Intel JHL9480 Barlow Ridge TB5 switch) over
         USB4, link 2 x 10 Gb/s
  GPU:   Intel Arc B580 12 GB, xe driver
  Kernel: 7.3.4 with v3 applied (it applies cleanly)

The firmware gives the USB4 root port 0000:00:03.1 a 64 GiB prefetchable
window, but the tunnel is enumerated as a hotplug event about 12 seconds
after boot, and without the patch the switch windows below it were sized
at 256 MiB, so the B580's BAR2 stayed at 256 MiB and a manual resize
failed.

With v3 the headroom is reserved down the chain:

  pci 0000:6a:01.0: bridge window [mem 0x400000000-0x40fffffff 64bit pref] to [bus 6b] add_size 3f0000000 add_align 400000000
  pci 0000:69:00.0: bridge window [mem 0x400000000-0x7ffffffff 64bit pref] to [bus 6a-6c] add_size 3f0000000 add_align 400000000

and xe then resizes the BAR when it binds:

  xe 0000:6b:00.0: [drm] Attempting to resize bar from 256MiB -> 16384MiB
  xe 0000:6b:00.0: [drm] BAR2 resized to 16384MiB

Both bridges above the GPU (69:00.0 and 6a:01.0) end up with 16 GiB
prefetchable windows, and the whole 12 GB of VRAM is CPU-visible. It has
been stable as a daily VAAPI/compute card since then. On 31 October I
also unplugged and re-plugged the dock while the system was running: it
re-enumerated, xe re-bound and BAR2 came back at 16 GiB.

One interaction that may be worth knowing about: with
pci=hpmmioprefsize=16G also on the command line, the TB5 switch's three
empty downstream (daisy-chain) ports each reserved 16 GiB as well. That
overflowed the 64 GiB root-port window, and the B580's BAR2 was briefly
assigned at 16 GiB and then rolled back with -ENOSPC. Without that
parameter it works as described above.

Tested-by: James R Taylor <jrtaylor11@gmail.com>

Thanks for the patch,
James