atmel nand bindings vs. actual dts files

[Alexander Dahl <ada@thorsis.com>]

Hei hei,

I'm currently adapting the at91-sama5d27_som1_ek.dts file for a custom 
modification of that board [1], and had a look at how sama5d3.dtsi, 
sama5d4.dtsi and boards including those define the nand controller and the 
nand chip. What puzzles me is the following. The atmel-nand devicetree binding 
docs say:


Required properties:
- reg: describes the CS lines assigned to the NAND device. If the NAND device
       exposes multiple CS lines (multi-dies chips), your reg property will
       contain X tuples of 3 entries.
       1st entry: the CS line this NAND chip is connected to
       2nd entry: the base offset of the memory region assigned to this
                  device (always 0)
       3rd entry: the memory region size (always 0x800000)


However the actual node of e.g. at91-sama5d3_xplained.dts contains this:

                                nand@3 {
                                        reg = <0x3 0x0 0x2>;
                                        atmel,rb = <0>;
                                        nand-bus-width = <8>;
                                        nand-ecc-mode = "hw";
                                        nand-ecc-strength = <4>;
                                        nand-ecc-step-size = <512>;
                                        nand-on-flash-bbt;

So instead of "always 0x800000" that node has 0x2 as third entry for the 'reg' 
property. Why is that?

Bonus question: if the R/B line is not connected, how is that expressed in 
dts? As far as I understood that is possible, if the driver polls some status 
register instead of that line level, right?

Greets
Alex

[1] we piggyback soldered a raw NAND flash to the som1 module with some 	
enameled copper wire for evaluation, NAND is already responding in a modified 
U-Boot ;-)

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