From: "Heiko Stübner" <heiko@sntech.de>
To: u-boot@lists.denx.de,
Alexandre Ghiti <alexandre.ghiti@canonical.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Coelacanthus <coelacanthus@outlook.com>,
Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>
Subject: Re: [PATCH] riscv: fix compitible with binutils 2.38
Date: Thu, 23 Jun 2022 15:42:45 +0200 [thread overview]
Message-ID: <1826121.tdWV9SEqCh@diego> (raw)
In-Reply-To: <PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB5594.namprd14.prod.outlook.com>
Hi,
Am Montag, 23. Mai 2022, 14:05:27 CEST schrieb Coelacanthus:
> commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 from linux kernel
>
> Since binutils 2.38, default ISA spec version switch to 20191213,
> in this version, original I extension be split into I, Zicsr and Zifencei.
> Zicsr is csr read/write (csrr*/csrw*) instructions, and Zifencei
> is fence.i instruction.
> This will cause compile error like this:
> Error: unrecognized opcode `csrr a5,0xc01'
> Error: unrecognized opcode `fence.i'
>
> This commit add code to detect new Zicsr and Zifencei extensions,
> and enable it when needed.
>
> Signed-off-by: Coelacanthus <coelacanthus@outlook.com>
> Cc: Rick Chen <rick@andestech.com>
> Cc: Leo <ycliang@andestech.com>
while this fixes the build issue I'm seeing after a recent binutils,
there has been already a patch proposed for this fix [0]
and in that thread some pending issue was discussed as well.
So please coordinate with the other people over there :-)
Thanks
Heiko
[0] https://lore.kernel.org/all/20220128134713.2322800-1-alexandre.ghiti@canonical.com/
> ---
> arch/riscv/Makefile | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 0b80eb8d86..62712f8d38 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -24,7 +24,14 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
> CMODEL = medany
> endif
>
> -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
> +RISCV_MARCH_y = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
> +
> +# Newer binutils versions default to ISA spec version 20191213 which moves some
> +# instructions from the I extension to the Zicsr and Zifencei extensions.
> +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH_y)_zicsr_zifencei)
> +RISCV_MARCH_$(toolchain-need-zicsr-zifencei) := $(RISCV_MARCH_y)_zicsr_zifencei
> +
> +ARCH_FLAGS = -march=$(RISCV_MARCH_y) -mabi=$(ABI) \
> -mcmodel=$(CMODEL)
>
> PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
>
next prev parent reply other threads:[~2022-06-23 13:42 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 12:05 [PATCH] riscv: fix compitible with binutils 2.38 Coelacanthus
2022-06-23 13:42 ` Heiko Stübner [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-05-27 2:36 [PULL] u-boot-riscv/master Leo Liang
2022-05-27 13:30 ` Tom Rini
2022-05-28 9:02 ` Leo Liang
2022-05-30 15:05 ` Tom Rini
2022-08-11 22:22 ` Leo Liang
2022-08-19 9:09 ` [PATCH] riscv: fix compitible with binutils 2.38 Leo Liang
2022-08-19 15:24 ` Simon Glass
2022-08-30 6:59 ` Leo Liang
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