From: "Rémi Denis-Courmont" <remi.denis.courmont@huawei.com>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 10/14] target/arm: do S1_ptw_translate() before address space lookup
Date: Tue, 03 Nov 2020 23:21:05 +0200 [thread overview]
Message-ID: <1855963.usQuhbGJ8B@basile.remlab.net> (raw)
In-Reply-To: <8ebcf033-7044-ee14-8b84-3812ff041d5c@linaro.org>
Le tiistaina 3. marraskuuta 2020, 21.54.48 EET Richard Henderson a écrit :
> On 11/2/20 2:57 AM, remi.denis.courmont@huawei.com wrote:
> > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> >
> > In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
> > bits can invert the secure flag for pagetable walks. This patchset
> > allows S1_ptw_translate() to change the non-secure bit.
> >
> > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> > ---
> >
> > target/arm/helper.c | 9 ++++++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/arm/helper.c b/target/arm/helper.c
> > index 4c86e4f57c..7c70460e65 100644
> > --- a/target/arm/helper.c
> > +++ b/target/arm/helper.c
> > @@ -10403,7 +10403,7 @@ static bool get_level1_table_address(CPUARMState
> > *env, ARMMMUIdx mmu_idx,>
> > /* Translate a S1 pagetable walk through S2 if needed. */
> > static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
> >
> > - hwaddr addr, MemTxAttrs txattrs,
> > + hwaddr addr, bool *is_secure,
> >
> > ARMMMUFaultInfo *fi)
> >
> > {
> >
> > ARMMMUIdx s2_mmu_idx;
> >
> > @@ -10415,6 +10415,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
> > ARMMMUIdx mmu_idx,>
> > int s2prot;
> > int ret;
> > ARMCacheAttrs cacheattrs = {};
> >
> > + MemTxAttrs txattrs = {};
> > +
> > + assert(!*is_secure); /* TODO: S-EL2 */
>
> Are you sure that you don't want to pass in txattrs via pointer instead?
That's possible too, and more like the existing code. Though I thought it
clearer to pass only a pointer to the secure bit in/out, seen as that's the
only in/out parameter.
> This change by itself looks questionable. I guess I'll have to look
> forward to the other patch...
--
Rémi Denis-Courmont
next prev parent reply other threads:[~2020-11-03 21:21 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <2172054.ElGaqSPkdT@basile.remlab.net>
2020-11-02 10:57 ` [PATCH 01/14] target/arm: add arm_is_el2_enabled() helper remi.denis.courmont
2020-11-02 11:06 ` Peter Maydell
2020-11-02 11:27 ` Peter Maydell
2020-11-02 13:35 ` Remi Denis Courmont
2020-11-03 16:42 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 02/14] target/arm: use arm_is_el2_enabled() where applicable remi.denis.courmont
2020-11-03 16:53 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 03/14] target/arm: use arm_hcr_el2_eff() " remi.denis.courmont
2020-11-03 16:56 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 04/14] target/arm: factor MDCR_EL2 common handling remi.denis.courmont
2020-11-03 17:00 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 05/14] target/arm: declare new AA64PFR0 bit-fields remi.denis.courmont
2020-11-03 17:02 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 06/14] target/arm: add 64-bit S-EL2 to EL exception table remi.denis.courmont
2020-11-02 10:57 ` [PATCH 07/14] target/arm: return the stage 2 index for stage 1 remi.denis.courmont
2020-11-03 17:04 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 08/14] target/arm: add MMU stage 1 for Secure EL2 remi.denis.courmont
2020-11-03 18:32 ` Richard Henderson
2020-11-03 18:49 ` Rémi Denis-Courmont
2020-11-03 19:41 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 09/14] target/arm: add ARMv8.4-SEL2 system registers remi.denis.courmont
2020-11-03 19:49 ` Richard Henderson
2020-11-03 21:09 ` Peter Maydell
2020-11-03 21:40 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 10/14] target/arm: do S1_ptw_translate() before address space lookup remi.denis.courmont
2020-11-03 19:54 ` Richard Henderson
2020-11-03 21:21 ` Rémi Denis-Courmont [this message]
2020-11-02 10:57 ` [PATCH 11/14] target/arm: secure stage 2 translation regime remi.denis.courmont
2020-11-02 10:58 ` [PATCH 12/14] target/arm: set HPFAR_EL2.NS on secure stage 2 faults remi.denis.courmont
2020-11-02 10:58 ` [PATCH 13/14] target/arm: add ARMv8.4-SEL2 extension remi.denis.courmont
2020-11-03 20:14 ` Richard Henderson
2020-11-02 10:58 ` [PATCH 14/14] target/arm: enable Secure EL2 in max CPU remi.denis.courmont
2020-11-03 7:38 ` Rémi Denis-Courmont
2020-11-03 16:38 ` Richard Henderson
2020-11-03 20:15 ` Richard Henderson
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