From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:38158 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726010AbeHTMjK (ORCPT ); Mon, 20 Aug 2018 08:39:10 -0400 From: Laurent Pinchart To: Ulrich Hecht Cc: linux-renesas-soc@vger.kernel.org, dri-devel@lists.freedesktop.org, jacopo+renesas@jmondi.org, kieran.bingham+renesas@ideasonboard.com, Koji Matsuoka Subject: Re: [PROTO][PATCH 03/10] drm: rcar-du: Fix digital RGB routing for R8A77995 Date: Mon, 20 Aug 2018 12:25:12 +0300 Message-ID: <1858666.BrqN8bjDtY@avalon> In-Reply-To: <1534254604-24204-4-git-send-email-uli+renesas@fpond.eu> References: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> <1534254604-24204-4-git-send-email-uli+renesas@fpond.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Ulrich, Thank you for the patch. On Tuesday, 14 August 2018 16:49:57 EEST Ulrich Hecht wrote: > From: Koji Matsuoka > > This patch adds D3 definition for DU and fixes digital RGB routing. > > Signed-off-by: Koji Matsuoka > --- > drivers/gpu/drm/rcar-du/rcar_du_drv.c | 3 ++- > drivers/gpu/drm/rcar-du/rcar_du_drv.h | 2 ++ > drivers/gpu/drm/rcar-du/rcar_du_group.c | 4 ++++ > 3 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 5c2f764..d930996 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c > @@ -298,7 +298,8 @@ static const struct rcar_du_device_info > rcar_du_r8a77995_info = { .gen = 3, > .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK > > | RCAR_DU_FEATURE_EXT_CTRL_REGS > > - | RCAR_DU_FEATURE_VSP1_SOURCE, > + | RCAR_DU_FEATURE_VSP1_SOURCE > + | RCAR_DU_FEATURE_R8A77995_REGS, > .quirks = RCAR_DU_QUIRK_TVM_MASTER_ONLY, > .channels_mask = BIT(1) | BIT(0), > .routes = { > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index 6257405..9355b58 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h > @@ -30,6 +30,8 @@ struct rcar_du_device; > #define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK (1 << 0) /* Per-CRTC IRQ and clock > */ #define RCAR_DU_FEATURE_EXT_CTRL_REGS (1 << 1) /* Has extended control > registers */ #define RCAR_DU_FEATURE_VSP1_SOURCE (1 << 2) /* Has inputs > from VSP1 */ +#define RCAR_DU_FEATURE_R8A77965_REGS (1 << 3) /* Use > R8A77965 registers */ +#define RCAR_DU_FEATURE_R8A77995_REGS (1 << 4) /* > Use R8A77995 registers */ > > #define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */ > #define RCAR_DU_QUIRK_TVM_MASTER_ONLY (1 << 1) /* Does not have TV > switch/sync modes */ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c > b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 9a0a694..371d780 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c > @@ -88,6 +88,10 @@ static void rcar_du_group_setup_defr8(struct > rcar_du_group *rgrp) > > if (crtc->index / 2 == rgrp->index) > defr8 |= DEFR8_DRGBS_DU(crtc->index); > + > + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_R8A77995_REGS)) > + defr8 |= (DEFR8_DRGBS_DU(rcdu->dpad0_source) | > + DEFR8_DRGBS_DU(crtc->index)); Does this need a special case ? Can't we replace the existing logic with code based on dpad0_source, and make sure that dpad0_source always contains the correct value on SoCs that have a hardcoded connection between DU and DPAD ? > } > > rcar_du_group_write(rgrp, DEFR8, defr8); -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PROTO][PATCH 03/10] drm: rcar-du: Fix digital RGB routing for R8A77995 Date: Mon, 20 Aug 2018 12:25:12 +0300 Message-ID: <1858666.BrqN8bjDtY@avalon> References: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> <1534254604-24204-4-git-send-email-uli+renesas@fpond.eu> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by gabe.freedesktop.org (Postfix) with ESMTPS id F055889A91 for ; Mon, 20 Aug 2018 09:24:18 +0000 (UTC) In-Reply-To: <1534254604-24204-4-git-send-email-uli+renesas@fpond.eu> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Ulrich Hecht Cc: linux-renesas-soc@vger.kernel.org, kieran.bingham+renesas@ideasonboard.com, jacopo+renesas@jmondi.org, Koji Matsuoka , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org SGkgVWxyaWNoLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpPbiBUdWVzZGF5LCAxNCBBdWd1 c3QgMjAxOCAxNjo0OTo1NyBFRVNUIFVscmljaCBIZWNodCB3cm90ZToKPiBGcm9tOiBLb2ppIE1h dHN1b2thIDxrb2ppLm1hdHN1b2thLnhtQHJlbmVzYXMuY29tPgo+IAo+IFRoaXMgcGF0Y2ggYWRk cyBEMyBkZWZpbml0aW9uIGZvciBEVSBhbmQgZml4ZXMgZGlnaXRhbCBSR0Igcm91dGluZy4KPiAK PiBTaWduZWQtb2ZmLWJ5OiBLb2ppIE1hdHN1b2thIDxrb2ppLm1hdHN1b2thLnhtQHJlbmVzYXMu Y29tPgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5jICAgfCAz ICsrLQo+ICBkcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5oICAgfCAyICsrCj4g IGRyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZ3JvdXAuYyB8IDQgKysrKwo+ICAzIGZp bGVzIGNoYW5nZWQsIDggaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQo+IAo+IGRpZmYgLS1n aXQgYS9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5jCj4gYi9kcml2ZXJzL2dw dS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5jIGluZGV4IDVjMmY3NjQuLmQ5MzA5OTYgMTAwNjQ0 Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9kcnYuYwo+ICsrKyBiL2Ry aXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmMKPiBAQCAtMjk4LDcgKzI5OCw4IEBA IHN0YXRpYyBjb25zdCBzdHJ1Y3QgcmNhcl9kdV9kZXZpY2VfaW5mbwo+IHJjYXJfZHVfcjhhNzc5 OTVfaW5mbyA9IHsgLmdlbiA9IDMsCj4gIAkuZmVhdHVyZXMgPSBSQ0FSX0RVX0ZFQVRVUkVfQ1JU Q19JUlFfQ0xPQ0sKPiAKPiAgCQkgIHwgUkNBUl9EVV9GRUFUVVJFX0VYVF9DVFJMX1JFR1MKPiAK PiAtCQkgIHwgUkNBUl9EVV9GRUFUVVJFX1ZTUDFfU09VUkNFLAo+ICsJCSAgfCBSQ0FSX0RVX0ZF QVRVUkVfVlNQMV9TT1VSQ0UKPiArCQkgIHwgUkNBUl9EVV9GRUFUVVJFX1I4QTc3OTk1X1JFR1Ms Cj4gIAkucXVpcmtzID0gUkNBUl9EVV9RVUlSS19UVk1fTUFTVEVSX09OTFksCj4gIAkuY2hhbm5l bHNfbWFzayA9IEJJVCgxKSB8IEJJVCgwKSwKPiAgCS5yb3V0ZXMgPSB7Cj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmgKPiBiL2RyaXZlcnMvZ3B1L2Ry bS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmggaW5kZXggNjI1NzQwNS4uOTM1NWI1OCAxMDA2NDQKPiAt LS0gYS9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5oCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9kcnYuaAo+IEBAIC0zMCw2ICszMCw4IEBAIHN0cnVj dCByY2FyX2R1X2RldmljZTsKPiAgI2RlZmluZSBSQ0FSX0RVX0ZFQVRVUkVfQ1JUQ19JUlFfQ0xP Q0sJKDEgPDwgMCkJLyogUGVyLUNSVEMgSVJRIGFuZCBjbG9jawo+ICovICNkZWZpbmUgUkNBUl9E VV9GRUFUVVJFX0VYVF9DVFJMX1JFR1MJKDEgPDwgMSkJLyogSGFzIGV4dGVuZGVkIGNvbnRyb2wK PiByZWdpc3RlcnMgKi8gI2RlZmluZSBSQ0FSX0RVX0ZFQVRVUkVfVlNQMV9TT1VSQ0UJKDEgPDwg MikJLyogSGFzIGlucHV0cwo+IGZyb20gVlNQMSAqLyArI2RlZmluZSBSQ0FSX0RVX0ZFQVRVUkVf UjhBNzc5NjVfUkVHUwkoMSA8PCAzKQkvKiBVc2UKPiBSOEE3Nzk2NSByZWdpc3RlcnMgKi8gKyNk ZWZpbmUgUkNBUl9EVV9GRUFUVVJFX1I4QTc3OTk1X1JFR1MJKDEgPDwgNCkJLyoKPiBVc2UgUjhB Nzc5OTUgcmVnaXN0ZXJzICovCj4gCj4gICNkZWZpbmUgUkNBUl9EVV9RVUlSS19BTElHTl8xMjhC CSgxIDw8IDApCS8qIEFsaWduIHBpdGNoZXMgdG8gMTI4IGJ5dGVzIAoqLwo+ICAjZGVmaW5lIFJD QVJfRFVfUVVJUktfVFZNX01BU1RFUl9PTkxZCSgxIDw8IDEpCS8qIERvZXMgbm90IGhhdmUgVFYK PiBzd2l0Y2gvc3luYyBtb2RlcyAqLyBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JjYXIt ZHUvcmNhcl9kdV9ncm91cC5jCj4gYi9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2dy b3VwLmMgaW5kZXggOWEwYTY5NC4uMzcxZDc4MCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9k cm0vcmNhci1kdS9yY2FyX2R1X2dyb3VwLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vcmNhci1k dS9yY2FyX2R1X2dyb3VwLmMKPiBAQCAtODgsNiArODgsMTAgQEAgc3RhdGljIHZvaWQgcmNhcl9k dV9ncm91cF9zZXR1cF9kZWZyOChzdHJ1Y3QKPiByY2FyX2R1X2dyb3VwICpyZ3JwKQo+IAo+ICAJ CWlmIChjcnRjLT5pbmRleCAvIDIgPT0gcmdycC0+aW5kZXgpCj4gIAkJCWRlZnI4IHw9IERFRlI4 X0RSR0JTX0RVKGNydGMtPmluZGV4KTsKPiArCj4gKwkJaWYgKHJjYXJfZHVfaGFzKHJjZHUsIFJD QVJfRFVfRkVBVFVSRV9SOEE3Nzk5NV9SRUdTKSkKPiArCQkJZGVmcjggfD0gKERFRlI4X0RSR0JT X0RVKHJjZHUtPmRwYWQwX3NvdXJjZSkgfAo+ICsJCQkJIERFRlI4X0RSR0JTX0RVKGNydGMtPmlu ZGV4KSk7CgpEb2VzIHRoaXMgbmVlZCBhIHNwZWNpYWwgY2FzZSA/IENhbid0IHdlIHJlcGxhY2Ug dGhlIGV4aXN0aW5nIGxvZ2ljIHdpdGggY29kZSAKYmFzZWQgb24gZHBhZDBfc291cmNlLCBhbmQg bWFrZSBzdXJlIHRoYXQgZHBhZDBfc291cmNlIGFsd2F5cyBjb250YWlucyB0aGUgCmNvcnJlY3Qg dmFsdWUgb24gU29DcyB0aGF0IGhhdmUgYSBoYXJkY29kZWQgY29ubmVjdGlvbiBiZXR3ZWVuIERV IGFuZCBEUEFEID8KCj4gIAl9Cj4gCj4gIAlyY2FyX2R1X2dyb3VwX3dyaXRlKHJncnAsIERFRlI4 LCBkZWZyOCk7CgotLSAKUmVnYXJkcywKCkxhdXJlbnQgUGluY2hhcnQKCgoKX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlz dApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0 b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==