diff for duplicates of <1868508.hOA6VOBqnH@diego> diff --git a/a/1.txt b/N1/1.txt index 3160dc1..598eef1 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Node definitions shared by all rk3288 based boards. -Signed-off-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> --- arch/arm/boot/dts/rk3288.dtsi | 561 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 561 insertions(+) @@ -40,22 +40,22 @@ index 0000000..6e36cec + #address-cells = <1>; + #size-cells = <0>; + -+ cpu at 0 { ++ cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x500>; + }; -+ cpu at 1 { ++ cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x501>; + }; -+ cpu at 2 { ++ cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x502>; + }; -+ cpu at 3 { ++ cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a12"; + reg = <0x503>; @@ -83,7 +83,7 @@ index 0000000..6e36cec + clock-frequency = <24000000>; + }; + -+ gic: interrupt-controller at ffc01000 { ++ gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; @@ -96,17 +96,17 @@ index 0000000..6e36cec + interrupts = <GIC_PPI 9 0xf04>; + }; + -+ pmu: pmu at ff730000 { ++ pmu: pmu@ff730000 { + compatible = "syscon"; + reg = <0xff730000 0x100>; + }; + -+ sgrf: syscon at ff740000 { ++ sgrf: syscon@ff740000 { + compatible = "syscon"; + reg = <0xff740000 0x1000>; + }; + -+ cru: cru at ff760000 { ++ cru: cru@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; @@ -115,12 +115,12 @@ index 0000000..6e36cec + #reset-cells = <1>; + }; + -+ grf: syscon at ff770000 { ++ grf: syscon@ff770000 { + compatible = "syscon"; + reg = <0xff770000 0x1000>; + }; + -+ pinctrl: pinctrl at ff770000 { ++ pinctrl: pinctrl@ff770000 { + compatible = "rockchip,rk3288-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; @@ -129,7 +129,7 @@ index 0000000..6e36cec + #size-cells = <1>; + ranges; + -+ gpio0: gpio0 at ff750000 { ++ gpio0: gpio0@ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff750000 0x100>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -142,7 +142,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio1: gpio1 at ff780000 { ++ gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff780000 0x100>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -155,7 +155,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio2: gpio2 at ff790000 { ++ gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff790000 0x100>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; @@ -168,7 +168,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio3: gpio3 at ff7a0000 { ++ gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7a0000 0x100>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; @@ -181,7 +181,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio4: gpio4 at ff7b0000 { ++ gpio4: gpio4@ff7b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7b0000 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -194,7 +194,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio5: gpio5 at ff7c0000 { ++ gpio5: gpio5@ff7c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7c0000 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -207,7 +207,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio6: gpio6 at ff7d0000 { ++ gpio6: gpio6@ff7d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7d0000 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -220,7 +220,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio7: gpio7 at ff7e0000 { ++ gpio7: gpio7@ff7e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7e0000 0x100>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; @@ -233,7 +233,7 @@ index 0000000..6e36cec + #interrupt-cells = <2>; + }; + -+ gpio8: gpio8 at ff7f0000 { ++ gpio8: gpio8@ff7f0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff7f0000 0x100>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; @@ -430,7 +430,7 @@ index 0000000..6e36cec + }; + }; + -+ i2c0: i2c at ff650000 { ++ i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff650000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -443,7 +443,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ i2c1: i2c at ff140000 { ++ i2c1: i2c@ff140000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff140000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -456,7 +456,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ i2c2: i2c at ff660000 { ++ i2c2: i2c@ff660000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff660000 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -469,7 +469,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ i2c3: i2c at ff150000 { ++ i2c3: i2c@ff150000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff150000 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; @@ -482,7 +482,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ i2c4: i2c at ff160000 { ++ i2c4: i2c@ff160000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff160000 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; @@ -495,7 +495,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ i2c5: i2c at ff170000 { ++ i2c5: i2c@ff170000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0xff170000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; @@ -508,14 +508,14 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ watchdog at ff800000 { ++ watchdog@ff800000 { + compatible = "snps,dw-wdt"; + reg = <0xff800000 0x100>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + -+ uart0: serial at ff180000 { ++ uart0: serial@ff180000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff180000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -526,7 +526,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ uart1: serial at ff190000 { ++ uart1: serial@ff190000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff190000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -537,7 +537,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ uart2: serial at ff690000 { ++ uart2: serial@ff690000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff690000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -550,7 +550,7 @@ index 0000000..6e36cec + pinctrl-0 = <&uart2_xfer>; + }; + -+ uart3: serial at ff1b0000 { ++ uart3: serial@ff1b0000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff1b0000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; @@ -561,7 +561,7 @@ index 0000000..6e36cec + status = "disabled"; + }; + -+ uart4: serial at ff1c0000 { ++ uart4: serial@ff1c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff1c0000 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; @@ -575,3 +575,9 @@ index 0000000..6e36cec +}; -- 1.9.0 + + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index bef1dff..a9cb98e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,17 @@ "ref\01471578.ILeMmG2DL6@diego\0" - "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0[PATCH 5/6] ARM: dts: rockchip: add core rk3288 dtsi\0" "Date\0Wed, 16 Jul 2014 01:02:20 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "Cc\0olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org" + dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org + eddie.cai-TNX95d0MmH7DzftRWevZcw@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Node definitions shared by all rk3288 based boards.\n" "\n" - "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" + "Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" "---\n" " arch/arm/boot/dts/rk3288.dtsi | 561 ++++++++++++++++++++++++++++++++++++++++++\n" " 1 file changed, 561 insertions(+)\n" @@ -47,22 +51,22 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu at 0 {\n" + "+\t\tcpu@0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x500>;\n" "+\t\t};\n" - "+\t\tcpu at 1 {\n" + "+\t\tcpu@1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x501>;\n" "+\t\t};\n" - "+\t\tcpu at 2 {\n" + "+\t\tcpu@2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x502>;\n" "+\t\t};\n" - "+\t\tcpu at 3 {\n" + "+\t\tcpu@3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a12\";\n" "+\t\t\treg = <0x503>;\n" @@ -90,7 +94,7 @@ "+\t\t\tclock-frequency = <24000000>;\n" "+\t\t};\n" "+\n" - "+\t\tgic: interrupt-controller at ffc01000 {\n" + "+\t\tgic: interrupt-controller@ffc01000 {\n" "+\t\t\tcompatible = \"arm,gic-400\";\n" "+\t\t\tinterrupt-controller;\n" "+\t\t\t#interrupt-cells = <3>;\n" @@ -103,17 +107,17 @@ "+\t\t\tinterrupts = <GIC_PPI 9 0xf04>;\n" "+\t\t};\n" "+\n" - "+\t\tpmu: pmu at ff730000 {\n" + "+\t\tpmu: pmu@ff730000 {\n" "+\t\t\tcompatible = \"syscon\";\n" "+\t\t\treg = <0xff730000 0x100>;\n" "+\t\t};\n" "+\n" - "+\t\tsgrf: syscon at ff740000 {\n" + "+\t\tsgrf: syscon@ff740000 {\n" "+\t\t\tcompatible = \"syscon\";\n" "+\t\t\treg = <0xff740000 0x1000>;\n" "+\t\t};\n" "+\n" - "+\t\tcru: cru at ff760000 {\n" + "+\t\tcru: cru@ff760000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-cru\";\n" "+\t\t\treg = <0xff760000 0x1000>;\n" "+\t\t\trockchip,grf = <&grf>;\n" @@ -122,12 +126,12 @@ "+\t\t\t#reset-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tgrf: syscon at ff770000 {\n" + "+\t\tgrf: syscon@ff770000 {\n" "+\t\t\tcompatible = \"syscon\";\n" "+\t\t\treg = <0xff770000 0x1000>;\n" "+\t\t};\n" "+\n" - "+\t\tpinctrl: pinctrl at ff770000 {\n" + "+\t\tpinctrl: pinctrl@ff770000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-pinctrl\";\n" "+\t\t\trockchip,grf = <&grf>;\n" "+\t\t\trockchip,pmu = <&pmu>;\n" @@ -136,7 +140,7 @@ "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges;\n" "+\n" - "+\t\t\tgpio0: gpio0 at ff750000 {\n" + "+\t\t\tgpio0: gpio0@ff750000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg =\t<0xff750000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -149,7 +153,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio1: gpio1 at ff780000 {\n" + "+\t\t\tgpio1: gpio1@ff780000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff780000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -162,7 +166,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio2: gpio2 at ff790000 {\n" + "+\t\t\tgpio2: gpio2@ff790000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff790000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -175,7 +179,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio3: gpio3 at ff7a0000 {\n" + "+\t\t\tgpio3: gpio3@ff7a0000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff7a0000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -188,7 +192,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio4: gpio4 at ff7b0000 {\n" + "+\t\t\tgpio4: gpio4@ff7b0000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff7b0000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -201,7 +205,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio5: gpio5 at ff7c0000 {\n" + "+\t\t\tgpio5: gpio5@ff7c0000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff7c0000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -214,7 +218,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio6: gpio6 at ff7d0000 {\n" + "+\t\t\tgpio6: gpio6@ff7d0000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff7d0000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -227,7 +231,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio7: gpio7 at ff7e0000 {\n" + "+\t\t\tgpio7: gpio7@ff7e0000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff7e0000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -240,7 +244,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio8: gpio8 at ff7f0000 {\n" + "+\t\t\tgpio8: gpio8@ff7f0000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0xff7f0000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -437,7 +441,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\ti2c0: i2c at ff650000 {\n" + "+\t\ti2c0: i2c@ff650000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\t\treg = <0xff650000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -450,7 +454,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\ti2c1: i2c at ff140000 {\n" + "+\t\ti2c1: i2c@ff140000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\t\treg = <0xff140000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -463,7 +467,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\ti2c2: i2c at ff660000 {\n" + "+\t\ti2c2: i2c@ff660000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\t\treg = <0xff660000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -476,7 +480,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\ti2c3: i2c at ff150000 {\n" + "+\t\ti2c3: i2c@ff150000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\t\treg = <0xff150000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -489,7 +493,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\ti2c4: i2c at ff160000 {\n" + "+\t\ti2c4: i2c@ff160000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\t\treg = <0xff160000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -502,7 +506,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\ti2c5: i2c at ff170000 {\n" + "+\t\ti2c5: i2c@ff170000 {\n" "+\t\t\tcompatible = \"rockchip,rk3288-i2c\";\n" "+\t\t\treg = <0xff170000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -515,14 +519,14 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\twatchdog at ff800000 {\n" + "+\t\twatchdog@ff800000 {\n" "+\t\t\tcompatible = \"snps,dw-wdt\";\n" "+\t\t\treg = <0xff800000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart0: serial at ff180000 {\n" + "+\t\tuart0: serial@ff180000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0xff180000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -533,7 +537,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart1: serial at ff190000 {\n" + "+\t\tuart1: serial@ff190000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0xff190000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -544,7 +548,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart2: serial at ff690000 {\n" + "+\t\tuart2: serial@ff690000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0xff690000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -557,7 +561,7 @@ "+\t\t\tpinctrl-0 = <&uart2_xfer>;\n" "+\t\t};\n" "+\n" - "+\t\tuart3: serial at ff1b0000 {\n" + "+\t\tuart3: serial@ff1b0000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0xff1b0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -568,7 +572,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart4: serial at ff1c0000 {\n" + "+\t\tuart4: serial@ff1c0000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0xff1c0000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -581,6 +585,12 @@ "+\t};\n" "+};\n" "-- \n" - 1.9.0 + "1.9.0\n" + "\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -4678ab806801d68a2fefc0d7abe216f302c30a80aab2b8363120ffd0e512fb76 +622fb26b795eed7526681c1d523a5a08b6700af0f7e503a9c655b87add91a016
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