diff for duplicates of <1871781.cSEoq02CXi@phil> diff --git a/a/1.txt b/N1/1.txt index 24750fc..1857636 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -124,7 +124,7 @@ please don't leave commented code around > + -> + cpu@f00 { +> + cpu at f00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf00>; @@ -137,7 +137,7 @@ please don't leave commented code around > + clocks = <&cru ARMCLK>; > + resets = <&cru SRST_CORE0>; > + }; -> + cpu@f01 { +> + cpu at f01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf01>; @@ -151,7 +151,7 @@ please don't leave commented code around > + #size-cells = <1>; > + ranges; > + -> + pdma: pdma@20078000 { +> + pdma: pdma at 20078000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x20078000 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -188,7 +188,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + always-on; > + }; > + -> + cru: clock-controller@20000000 { +> + cru: clock-controller at 20000000 { > + compatible = "rockchip,rk3036-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; @@ -198,7 +198,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + assigned-clock-rates = <594000000>; > + }; > + -> + uart0: serial@20060000 { +> + uart0: serial at 20060000 { > + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; > + reg = <0x20060000 0x100>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -211,7 +211,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; > + }; > + -> + uart1: serial@20064000 { +> + uart1: serial at 20064000 { > + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; > + reg = <0x20064000 0x100>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; @@ -224,7 +224,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + pinctrl-0 = <&uart1_xfer>; > + }; > + -> + uart2: serial@20068000 { +> + uart2: serial at 20068000 { > + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; > + reg = <0x20068000 0x100>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -237,7 +237,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + pinctrl-0 = <&uart2_xfer>; > + }; > + -> + pwm0: pwm@20050000 { +> + pwm0: pwm at 20050000 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050000 0x10>; > + #pwm-cells = <3>; @@ -248,7 +248,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + status = "disabled"; > + }; > + -> + pwm1: pwm@20050010 { +> + pwm1: pwm at 20050010 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050010 0x10>; > + #pwm-cells = <3>; @@ -259,7 +259,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + status = "disabled"; > + }; > + -> + pwm2: pwm@20050020 { +> + pwm2: pwm at 20050020 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050020 0x10>; > + #pwm-cells = <3>; @@ -270,7 +270,7 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + status = "disabled"; > + }; > + -> + pwm3: pwm@20050030 { +> + pwm3: pwm at 20050030 { > + compatible = "rockchip,rk2928-pwm"; > + reg = <0x20050030 0x10>; > + #pwm-cells = <2>; @@ -281,13 +281,13 @@ please provide all 4 irqs (secure, non-secure, virtual and hypervisor) > + status = "disabled"; > + }; > + -> + sram@10080000 { +> + sram at 10080000 { > + compatible = "mmio-sram"; > + reg = <0x10080000 0x2000>; > + map-exec; > + }; > + -> + gic: interrupt-controller@10139000 { +> + gic: interrupt-controller at 10139000 { > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -301,7 +301,7 @@ please also provide the vgic registers and interrupt > + }; > + -> + grf: syscon@20008000 { +> + grf: syscon at 20008000 { > + compatible = "rockchip,rk3036-grf", "syscon"; > + reg = <0x20008000 0x1000>; > + }; @@ -313,7 +313,7 @@ please also provide the vgic registers and interrupt > + #size-cells = <1>; > + ranges; > + -> + gpio0: gpio0@2007c000 { +> + gpio0: gpio0 at 2007c000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x2007c000 0x100>; @@ -330,7 +330,7 @@ please use a space after the "=" in "reg = <..." > + #interrupt-cells = <2>; > + }; > + -> + gpio1: gpio1@20080000 { +> + gpio1: gpio1 at 20080000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x20080000 0x100>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -343,7 +343,7 @@ please use a space after the "=" in "reg = <..." > + #interrupt-cells = <2>; > + }; > + -> + gpio2: gpio2@20084000 { +> + gpio2: gpio2 at 20084000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x20084000 0x100>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index ab4d667..1a52ed6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,9 @@ "ref\01440740808-15004-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01440740808-15004-2-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v1 1/3] ARM: dts: rockchip: add core rk3036 dts\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[PATCH v1 1/3] ARM: dts: rockchip: add core rk3036 dts\0" "Date\0Fri, 28 Aug 2015 10:59:32 +0200\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - Mark Rutland <mark.rutland@arm.com> - Ian Campbell <ijc+devicetree@hellion.org.uk> - Kumar Gala <galak@codeaurora.org> - Russell King <linux@arm.linux.org.uk> - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -142,7 +132,7 @@ "\n" "\n" "> +\n" - "> +\t\tcpu@f00 {\n" + "> +\t\tcpu at f00 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf00>;\n" @@ -155,7 +145,7 @@ "> +\t\t\tclocks = <&cru ARMCLK>;\n" "> +\t\t\tresets = <&cru SRST_CORE0>;\n" "> +\t\t};\n" - "> +\t\tcpu@f01 {\n" + "> +\t\tcpu at f01 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf01>;\n" @@ -169,7 +159,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> + pdma: pdma@20078000 {\n" + "> + pdma: pdma at 20078000 {\n" "> + compatible = \"arm,pl330\", \"arm,primecell\";\n" "> + reg = <0x20078000 0x4000>;\n" "> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -206,7 +196,7 @@ "> +\t\talways-on;\n" "> +\t};\n" "> +\n" - "> +\tcru: clock-controller@20000000 {\n" + "> +\tcru: clock-controller at 20000000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-cru\";\n" "> +\t\treg = <0x20000000 0x1000>;\n" "> +\t\trockchip,grf = <&grf>;\n" @@ -216,7 +206,7 @@ "> +\t\tassigned-clock-rates = <594000000>;\n" "> +\t};\n" "> +\n" - "> +\tuart0: serial@20060000 {\n" + "> +\tuart0: serial at 20060000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x20060000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -229,7 +219,7 @@ "> +\t\tpinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;\n" "> +\t};\n" "> +\n" - "> +\tuart1: serial@20064000 {\n" + "> +\tuart1: serial at 20064000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x20064000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -242,7 +232,7 @@ "> +\t\tpinctrl-0 = <&uart1_xfer>;\n" "> +\t};\n" "> +\n" - "> +\tuart2: serial@20068000 {\n" + "> +\tuart2: serial at 20068000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-uart\", \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x20068000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -255,7 +245,7 @@ "> +\t\tpinctrl-0 = <&uart2_xfer>;\n" "> +\t};\n" "> +\n" - "> +\tpwm0: pwm@20050000 {\n" + "> +\tpwm0: pwm at 20050000 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050000 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -266,7 +256,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm1: pwm@20050010 {\n" + "> +\tpwm1: pwm at 20050010 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050010 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -277,7 +267,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm2: pwm@20050020 {\n" + "> +\tpwm2: pwm at 20050020 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050020 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -288,7 +278,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm3: pwm@20050030 {\n" + "> +\tpwm3: pwm at 20050030 {\n" "> +\t\tcompatible = \"rockchip,rk2928-pwm\";\n" "> +\t\treg = <0x20050030 0x10>;\n" "> +\t\t#pwm-cells = <2>;\n" @@ -299,13 +289,13 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tsram@10080000 {\n" + "> +\tsram at 10080000 {\n" "> +\t\tcompatible = \"mmio-sram\";\n" "> +\t\treg = <0x10080000 0x2000>;\n" "> +\t\tmap-exec;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@10139000 {\n" + "> +\tgic: interrupt-controller at 10139000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\tinterrupt-controller;\n" "> +\t\t#interrupt-cells = <3>;\n" @@ -319,7 +309,7 @@ "\n" "> +\t};\n" "> +\n" - "> +\tgrf: syscon@20008000 {\n" + "> +\tgrf: syscon at 20008000 {\n" "> +\t\tcompatible = \"rockchip,rk3036-grf\", \"syscon\";\n" "> +\t\treg = <0x20008000 0x1000>;\n" "> +\t};\n" @@ -331,7 +321,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tgpio0: gpio0@2007c000 {\n" + "> +\t\tgpio0: gpio0 at 2007c000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg =\t<0x2007c000 0x100>;\n" "\n" @@ -348,7 +338,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio1@20080000 {\n" + "> +\t\tgpio1: gpio1 at 20080000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x20080000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -361,7 +351,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio2@20084000 {\n" + "> +\t\tgpio2: gpio2 at 20084000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x20084000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -454,4 +444,4 @@ "> +\t};\n" > +}; -4f26082e68c40c9732c03bfc34a83d304e4ee17c5396bd422708b77a97a52719 +a7e99725c0b7621f9cba291cd992a0ae44b241d617286c892975472cd49e249a
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