From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Samuel Holland <samuel@sholland.org>,
Andre Przywara <andre.przywara@arm.com>
Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/7] pinctrl: sunxi: refactor pinctrl variants into flags
Date: Sat, 18 Jan 2025 11:07:36 +0100 [thread overview]
Message-ID: <1881692.atdPhlSkOF@jernej-laptop> (raw)
In-Reply-To: <20241111005750.13071-2-andre.przywara@arm.com>
Dne ponedeljek, 11. november 2024 ob 01:57:44 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> For some Allwinner SoCs we have one pinctrl driver caring for multiple
> very similar chips, and are tagging certain pins with a variant bitmask.
> The Allwinner D1 introduced a slightly extended register layout, and we
> were abusing this variant mask to convey this bit of information into
> the common code part.
> Now there will be more pinctrl device properties to consider (has PortF
> voltage switch, for instance), so shoehorning this into the variant
> bitmask will not fly anymore.
>
> Refactor the "variant" field into a more generic "flags" field. It turns
> out that we don't need the variant bits to be unique across all SoCs,
> but only among those SoCs that share one driver (table), of which there
> are at most three variants at the moment. So the actual variant field can
> be limited to say 8 bits, and the other bits in the flag register can be
> re-purposed to hold other information, like this extended register
> layout.
> As a side effect we can move the variant definition into the per-SoC
> pinctrl driver file, which makes it more obvious that this is just a
> private definition, only relevant for this particular table.
> This also changes the artificial sun20i-d1 "variant" into the actual
> flag bit that we are after.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
That looks pretty neat cleanup.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
next prev parent reply other threads:[~2025-01-18 10:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-11 0:57 [PATCH 0/7] pinctrl: sunxi: Add Allwinner A523 support Andre Przywara
2024-11-11 0:57 ` [PATCH 1/7] pinctrl: sunxi: refactor pinctrl variants into flags Andre Przywara
2025-01-18 10:07 ` Jernej Škrabec [this message]
2024-11-11 0:57 ` [PATCH 2/7] pinctrl: sunxi: move bank K register offset Andre Przywara
2024-11-11 0:57 ` [PATCH 3/7] pinctrl: sunxi: support moved power configuration registers Andre Przywara
2024-11-11 0:57 ` [PATCH 4/7] pinctrl: sunxi: allow reading mux values from DT Andre Przywara
2024-11-11 0:57 ` [PATCH 5/7] dt-bindings: pinctrl: add compatible for Allwinner A523/T527 Andre Przywara
2024-11-12 15:38 ` Rob Herring
2024-11-13 8:50 ` Chen-Yu Tsai
2024-11-20 10:12 ` Andre Przywara
2025-01-14 7:01 ` Chen-Yu Tsai
2025-01-14 11:21 ` Andre Przywara
2025-01-14 14:21 ` Chen-Yu Tsai
2024-11-11 0:57 ` [PATCH 6/7] pinctrl: sunxi: Add support for the Allwinner A523 Andre Przywara
2024-11-11 0:57 ` [PATCH 7/7] pinctrl: sunxi: Add support for the secondary A523 GPIO ports Andre Przywara
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