From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F02C3C25B75 for ; Mon, 3 Jun 2024 12:45:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 859D910E0C8; Mon, 3 Jun 2024 12:45:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=tq-group.com header.i=@tq-group.com header.b="eUEG0BkC"; dkim=fail reason="key not found in DNS" (0-bit key; unprotected) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="K8Yw5b9K"; dkim-atps=neutral Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BACC10E0C8 for ; Mon, 3 Jun 2024 12:45:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1717418748; x=1748954748; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wDcKIoxzmqBV8Lf97CkNEAnIgzZns2Rn9+6zzj2a3gM=; b=eUEG0BkCEpP5A2F9UYozhmBbXxx8PLzwyMsqSDdfMtOB2XiG85IH8ViG ldI426X2DU+ZNSyGSByZlPyreMYGi1ySxteeBzQ5ACP/+0muh93fL5lMz tcCpZQBKDKaQ/ZHIA5eJnhD+xmkfV3AUaiJ2TFG6q+BkwMkAZire3LsFO D02gXQmvtFQiJkqgHf7kdGzTy16rN7UeyDVVTE4b/u3RyryuSDEybUmEo SUOcVijVu+QB5hkxHQOUgI3K4xLhMEPIK18/s7GLQBbNJSj0LhNeBxwKQ 5faSiqELefPdlAdRZopmdNJsdH5n5SGpHQtczfRbotQhx/m1kqCJTKgMs g==; X-CSE-ConnectionGUID: 3CeLuWAHQeS8rSMertxspw== X-CSE-MsgGUID: qaKZtFgVSVeDQuVpW1eY7g== X-IronPort-AV: E=Sophos;i="6.08,211,1712613600"; d="scan'208";a="37190103" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 03 Jun 2024 14:45:45 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F1B1316591E; Mon, 3 Jun 2024 14:45:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1717418741; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=wDcKIoxzmqBV8Lf97CkNEAnIgzZns2Rn9+6zzj2a3gM=; b=K8Yw5b9K1BW4rehbCbXposgpkvUAG5EgiVGalyDOQOerA67LIYrWcJjjS40cxV2kv47XO/ HupbKm6u/GgsJ97LD6n+hhQo72R4gdxoE9X88Z8vDJbBRpcfT4TN3RIB8vlmdV0dcWjNh7 wkxvG6pH+LNVbFUPoK+APj5l6frsNP5DILuxIvnPeYJltp4zdgZhtfKW+hXy2FGdX0k+Qo o9qiwQL/QOW9cAnS+KaqadQ3JAJ+z9K8+FN/HJC6kJzdxTAvyqxZsmBinau7orm+I9EtWx HF+OXEH3GWCBfgOeimXrNRYwwoDDLR2mOj/3gKoJ/J4eELV52OqxdMzGjap0Jg== From: Alexander Stein To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Andrzej Hajda , Daniel Vetter , David Airlie , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Lucas Stach , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , kernel@dh-electronics.com, Marek Vasut Subject: Re: [PATCH 2/6] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock Date: Mon, 03 Jun 2024 14:45:38 +0200 Message-ID: <1891607.tdWV9SEqCh@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20240531204130.277800-2-marex@denx.de> References: <20240531204130.277800-1-marex@denx.de> <20240531204130.277800-2-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Marek, Am Freitag, 31. Mai 2024, 22:39:48 CEST schrieb Marek Vasut: > Use tc_pxl_pll_calc() to find out the exact clock frequency generated by = the > Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency a= nd > pass it down the display pipeline to obtain exactly this frequency on inp= ut > into this bridge. >=20 > The precise input frequency that matches the Pixel PLL frequency is > important for this bridge, as if the frequencies do not match, the > bridge does suffer VFIFO overruns or underruns. >=20 > Signed-off-by: Marek Vasut > --- > Cc: Andrzej Hajda > Cc: Daniel Vetter > Cc: David Airlie > Cc: Jernej Skrabec > Cc: Jonas Karlman > Cc: Laurent Pinchart > Cc: Lucas Stach > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Thomas Zimmermann > Cc: dri-devel@lists.freedesktop.org > Cc: kernel@dh-electronics.com > --- > drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) >=20 > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/t= c358767.c > index 45af31414ce48..252cc08dcc4a8 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *= bridge, > struct drm_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > { > + struct tc_data *tc =3D bridge_to_tc(bridge); > + int adjusted_clock =3D 0; > + int ret; > + > + ret =3D tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), > + crtc_state->adjusted_mode.clock * 1000, > + &adjusted_clock, NULL); > + if (ret) > + return ret; > + > + crtc_state->adjusted_mode.clock =3D adjusted_clock / 1000; > + > /* DSI->DPI interface clock limitation: upto 100 MHz */ > if (crtc_state->adjusted_mode.clock > 100000) > return -EINVAL; > @@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *= bridge, > struct drm_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > { > + struct tc_data *tc =3D bridge_to_tc(bridge); > + int adjusted_clock =3D 0; > + int ret; > + > + ret =3D tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), > + crtc_state->adjusted_mode.clock * 1000, > + &adjusted_clock, NULL); > + if (ret) > + return ret; > + > + crtc_state->adjusted_mode.clock =3D adjusted_clock / 1000; This is prone to rounding errors. Debug output in my case: > [ 16.007127] tc358767 1-000f: enable video stream > [ 16.007148] tc358767 1-000f: PLL: requested 148500000 pixelclock, ref = 26000000 > [ 16.007163] tc358767 1-000f: PLL: got 147333333, delta -1166667 > [ 16.007169] tc358767 1-000f: PLL: 26000000 / 1 / 1 * 17 / 3 > [ 16.027112] tc358767 1-000f: set mode 1920x1080 > [ 16.027138] tc358767 1-000f: H margin 148,88 sync 44 > [ 16.027144] tc358767 1-000f: V margin 36,4 sync 5 > [ 16.027150] tc358767 1-000f: total: 2200x1125 > [ 16.059426] tc358767 1-000f: PLL: requested 147333000 pixelclock, ref = 26000000 > [ 16.059455] tc358767 1-000f: PLL: got 146250000, delta -1083000 > [ 16.059461] tc358767 1-000f: PLL: 26000000 / 1 / 4 * 45 / 2 > [ 16.095724] tc358767 1-000f: PLL: requested 146250000 pixelclock, ref = 26000000 > [ 16.095739] tc358767 1-000f: PLL: got 146250000, delta 0 > [ 16.095745] tc358767 1-000f: PLL: 26000000 / 1 / 4 * 45 / 2 The accuracy degrades with each call, until a full kHz frequency is reached, because drm_display_mode.clock only accounts for kHz, but the PLL calculation takes Hz into account. BTW: Which platform are you testing on? Best regards, Alexander > + > /* DPI->(e)DP interface clock limitation: upto 154 MHz */ > if (crtc_state->adjusted_mode.clock > 154000) > return -EINVAL; >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/