From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from galahad.ideasonboard.com ([185.26.127.97]:58660 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161247AbeBNRxO (ORCPT ); Wed, 14 Feb 2018 12:53:14 -0500 From: Laurent Pinchart To: Sergei Shtylyov Cc: David Airlie , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Mark Rutland Subject: Re: [PATCH 3/3] drm: rcar-du: lvds: add R8A77970 support Date: Wed, 14 Feb 2018 19:53:47 +0200 Message-ID: <1916253.7gD2R49gcv@avalon> In-Reply-To: <20180119183557.226328412@cogentembedded.com> References: <20180119183557.226328412@cogentembedded.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Sergei, Thank you for the patch. On Friday, 19 January 2018 20:29:21 EET Sergei Shtylyov wrote: > Add support for the R-Car V3M (R8A77970) SoC to the LVDS encoder driver. > Note that there are some differences with the other R-Car gen3 SoCs, e.g. > LVDPLLCR has the same layout as in the R-Car gen2 SoCs... > > Signed-off-by: Sergei Shtylyov > > --- > drivers/gpu/drm/rcar-du/rcar_lvds.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > Index: linux/drivers/gpu/drm/rcar-du/rcar_lvds.c > =================================================================== > --- linux.orig/drivers/gpu/drm/rcar-du/rcar_lvds.c > +++ linux/drivers/gpu/drm/rcar-du/rcar_lvds.c > @@ -32,6 +32,10 @@ enum rcar_lvds_mode { > }; > > #define RCAR_LVDS_QUIRK_LANES (1 << 0) /* LVDS lanes 1 and 3 inverted */ > +#define RCAR_LVDS_QUIRK_GEN2_PLLCR (1 << 1) /* LVDPLLCR has gen2-like */ > + /* layout on R8A77970 */ > +#define RCAR_LVDS_QUIRK_PHY (1 << 2) /* LVDS has PHY on R8A77970 */ > + /* and R8A7799{0|5} */ I'm not sure if that's the right explanation for this quirk. I assume the LVDS encoder to always have a PHY. The difference here is that it needs to be explicitly enabled. Note that the LVEN bit also exists in Gen2. > struct rcar_lvds_device_info { > unsigned int gen; > @@ -162,6 +166,7 @@ static void rcar_lvds_enable(struct drm_ > */ > struct drm_crtc *crtc = lvds->bridge.encoder->crtc; > const struct drm_display_mode *mode = &lvds->display_mode; > + unsigned int quirks = lvds->info->quirks; > unsigned int gen = lvds->info->gen; > u32 lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT; > u32 lvdpllcr; > @@ -186,7 +191,7 @@ static void rcar_lvds_enable(struct drm_ > LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC | > LVDCTRCR_CTR0SEL_HSYNC); > > - if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES) > + if (quirks & RCAR_LVDS_QUIRK_LANES) > lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3) > > | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1); > > else > @@ -195,7 +200,7 @@ static void rcar_lvds_enable(struct drm_ > rcar_lvds_write(lvds, LVDCHCR, lvdhcr); > > /* PLL clock configuration */ > - if (gen < 3) > + if (gen < 3 || quirks & RCAR_LVDS_QUIRK_GEN2_PLLCR) I'd set the RCAR_LVDS_QUIRK_GEN2_PLLCR flag in all the Gen2 rcar_lvds_device_info instances, and remove the gen check here. > lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock); > else > lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock); > @@ -227,6 +232,12 @@ static void rcar_lvds_enable(struct drm_ > rcar_lvds_write(lvds, LVDCR0, lvdcr0); > } > > + if (quirks & RCAR_LVDS_QUIRK_PHY) { > + /* Turn on the LVDS PHY. */ > + lvdcr0 |= LVDCR0_LVEN; > + rcar_lvds_write(lvds, LVDCR0, lvdcr0); > + } > + > /* Wait for the startup delay. */ > usleep_range(100, 150); > > @@ -499,6 +510,11 @@ static const struct rcar_lvds_device_inf > .gen = 3, > }; > > +static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { > + .gen = 3, > + .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_PHY, > +}; > + > static const struct of_device_id rcar_lvds_of_table[] = { > { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info }, > { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info }, > @@ -506,6 +522,7 @@ static const struct of_device_id rcar_lv > { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info }, > { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info }, > { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info }, > + { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info > }, { } > }; -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 3/3] drm: rcar-du: lvds: add R8A77970 support Date: Wed, 14 Feb 2018 19:53:47 +0200 Message-ID: <1916253.7gD2R49gcv@avalon> References: <20180119183557.226328412@cogentembedded.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from galahad.ideasonboard.com (galahad.ideasonboard.com [185.26.127.97]) by gabe.freedesktop.org (Postfix) with ESMTPS id 77AB86E467 for ; Wed, 14 Feb 2018 17:53:14 +0000 (UTC) In-Reply-To: <20180119183557.226328412@cogentembedded.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sergei Shtylyov Cc: David Airlie , linux-renesas-soc@vger.kernel.org, Mark Rutland , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org SGkgU2VyZ2VpLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpPbiBGcmlkYXksIDE5IEphbnVh cnkgMjAxOCAyMDoyOToyMSBFRVQgU2VyZ2VpIFNodHlseW92IHdyb3RlOgo+IEFkZCBzdXBwb3J0 IGZvciB0aGUgUi1DYXIgVjNNIChSOEE3Nzk3MCkgU29DIHRvIHRoZSBMVkRTIGVuY29kZXIgZHJp dmVyLgo+IE5vdGUgdGhhdCB0aGVyZSBhcmUgc29tZSBkaWZmZXJlbmNlcyB3aXRoIHRoZSBvdGhl ciBSLUNhciBnZW4zIFNvQ3MsIGUuZy4KPiBMVkRQTExDUiBoYXMgdGhlIHNhbWUgbGF5b3V0IGFz IGluIHRoZSBSLUNhciBnZW4yIFNvQ3MuLi4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBTZXJnZWkgU2h0 eWx5b3YgPHNlcmdlaS5zaHR5bHlvdkBjb2dlbnRlbWJlZGRlZC5jb20+Cj4gCj4gLS0tCj4gIGRy aXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfbHZkcy5jIHwgICAyMSArKysrKysrKysrKysrKysr KysrLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDE5IGluc2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0p Cj4gCj4gSW5kZXg6IGxpbnV4L2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfbHZkcy5jCj4g PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PQo+IC0tLSBsaW51eC5vcmlnL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJf bHZkcy5jCj4gKysrIGxpbnV4L2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfbHZkcy5jCj4g QEAgLTMyLDYgKzMyLDEwIEBAIGVudW0gcmNhcl9sdmRzX21vZGUgewo+ICB9Owo+IAo+ICAjZGVm aW5lIFJDQVJfTFZEU19RVUlSS19MQU5FUwkoMSA8PCAwKQkvKiBMVkRTIGxhbmVzIDEgYW5kIDMg aW52ZXJ0ZWQgKi8KPiArI2RlZmluZSBSQ0FSX0xWRFNfUVVJUktfR0VOMl9QTExDUiAoMSA8PCAx KQkvKiBMVkRQTExDUiBoYXMgZ2VuMi1saWtlICovCj4gKwkJCQkJCS8qIGxheW91dCBvbiBSOEE3 Nzk3MCAqLwo+ICsjZGVmaW5lIFJDQVJfTFZEU19RVUlSS19QSFkJKDEgPDwgMikJLyogTFZEUyBo YXMgUEhZIG9uIFI4QTc3OTcwICovCj4gKwkJCQkJCS8qIGFuZCAgUjhBNzc5OXswfDV9ICovCgpJ J20gbm90IHN1cmUgaWYgdGhhdCdzIHRoZSByaWdodCBleHBsYW5hdGlvbiBmb3IgdGhpcyBxdWly ay4gSSBhc3N1bWUgdGhlIExWRFMgCmVuY29kZXIgdG8gYWx3YXlzIGhhdmUgYSBQSFkuIFRoZSBk aWZmZXJlbmNlIGhlcmUgaXMgdGhhdCBpdCBuZWVkcyB0byBiZSAKZXhwbGljaXRseSBlbmFibGVk LiBOb3RlIHRoYXQgdGhlIExWRU4gYml0IGFsc28gZXhpc3RzIGluIEdlbjIuCgo+ICBzdHJ1Y3Qg cmNhcl9sdmRzX2RldmljZV9pbmZvIHsKPiAgCXVuc2lnbmVkIGludCBnZW47Cj4gQEAgLTE2Miw2 ICsxNjYsNyBAQCBzdGF0aWMgdm9pZCByY2FyX2x2ZHNfZW5hYmxlKHN0cnVjdCBkcm1fCj4gIAkg Ki8KPiAgCXN0cnVjdCBkcm1fY3J0YyAqY3J0YyA9IGx2ZHMtPmJyaWRnZS5lbmNvZGVyLT5jcnRj Owo+ICAJY29uc3Qgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUgPSAmbHZkcy0+ZGlzcGxh eV9tb2RlOwo+ICsJdW5zaWduZWQgaW50IHF1aXJrcyA9IGx2ZHMtPmluZm8tPnF1aXJrczsKPiAg CXVuc2lnbmVkIGludCBnZW4gPSBsdmRzLT5pbmZvLT5nZW47Cj4gIAl1MzIgbHZkY3IwID0gbHZk cy0+bW9kZSA8PCBMVkRDUjBfTFZNRF9TSElGVDsKPiAgCXUzMiBsdmRwbGxjcjsKPiBAQCAtMTg2 LDcgKzE5MSw3IEBAIHN0YXRpYyB2b2lkIHJjYXJfbHZkc19lbmFibGUoc3RydWN0IGRybV8KPiAg CQkJTFZEQ1RSQ1JfQ1RSMlNFTF9ESVNQIHwgTFZEQ1RSQ1JfQ1RSMVNFTF9WU1lOQyB8Cj4gIAkJ CUxWRENUUkNSX0NUUjBTRUxfSFNZTkMpOwo+IAo+IC0JaWYgKGx2ZHMtPmluZm8tPnF1aXJrcyAm IFJDQVJfTFZEU19RVUlSS19MQU5FUykKPiArCWlmIChxdWlya3MgJiBSQ0FSX0xWRFNfUVVJUktf TEFORVMpCj4gIAkJbHZkaGNyID0gTFZEQ0hDUl9DSFNFTF9DSCgwLCAwKSB8IExWRENIQ1JfQ0hT RUxfQ0goMSwgMykKPiAKPiAgCQkgICAgICAgfCBMVkRDSENSX0NIU0VMX0NIKDIsIDIpIHwgTFZE Q0hDUl9DSFNFTF9DSCgzLCAxKTsKPiAKPiAgCWVsc2UKPiBAQCAtMTk1LDcgKzIwMCw3IEBAIHN0 YXRpYyB2b2lkIHJjYXJfbHZkc19lbmFibGUoc3RydWN0IGRybV8KPiAgCXJjYXJfbHZkc193cml0 ZShsdmRzLCBMVkRDSENSLCBsdmRoY3IpOwo+IAo+ICAJLyogUExMIGNsb2NrIGNvbmZpZ3VyYXRp b24gKi8KPiAtCWlmIChnZW4gPCAzKQo+ICsJaWYgKGdlbiA8IDMgfHwgcXVpcmtzICYgUkNBUl9M VkRTX1FVSVJLX0dFTjJfUExMQ1IpCgpJJ2Qgc2V0IHRoZSBSQ0FSX0xWRFNfUVVJUktfR0VOMl9Q TExDUiBmbGFnIGluIGFsbCB0aGUgR2VuMiAKcmNhcl9sdmRzX2RldmljZV9pbmZvIGluc3RhbmNl cywgYW5kIHJlbW92ZSB0aGUgZ2VuIGNoZWNrIGhlcmUuCgo+ICAJCWx2ZHBsbGNyID0gcmNhcl9s dmRzX2x2ZHBsbGNyX2dlbjIobW9kZS0+Y2xvY2spOwo+ICAJZWxzZQo+ICAJCWx2ZHBsbGNyID0g cmNhcl9sdmRzX2x2ZHBsbGNyX2dlbjMobW9kZS0+Y2xvY2spOwo+IEBAIC0yMjcsNiArMjMyLDEy IEBAIHN0YXRpYyB2b2lkIHJjYXJfbHZkc19lbmFibGUoc3RydWN0IGRybV8KPiAgCQlyY2FyX2x2 ZHNfd3JpdGUobHZkcywgTFZEQ1IwLCBsdmRjcjApOwo+ICAJfQo+IAo+ICsJaWYgKHF1aXJrcyAm IFJDQVJfTFZEU19RVUlSS19QSFkpIHsKPiArCQkvKiBUdXJuIG9uIHRoZSBMVkRTIFBIWS4gKi8K PiArCQlsdmRjcjAgfD0gTFZEQ1IwX0xWRU47Cj4gKwkJcmNhcl9sdmRzX3dyaXRlKGx2ZHMsIExW RENSMCwgbHZkY3IwKTsKPiArCX0KPiArCj4gIAkvKiBXYWl0IGZvciB0aGUgc3RhcnR1cCBkZWxh eS4gKi8KPiAgCXVzbGVlcF9yYW5nZSgxMDAsIDE1MCk7Cj4gCj4gQEAgLTQ5OSw2ICs1MTAsMTEg QEAgc3RhdGljIGNvbnN0IHN0cnVjdCByY2FyX2x2ZHNfZGV2aWNlX2luZgo+ICAJLmdlbiA9IDMs Cj4gIH07Cj4gCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcmNhcl9sdmRzX2RldmljZV9pbmZvIHJj YXJfbHZkc19yOGE3Nzk3MF9pbmZvID0gewo+ICsJLmdlbiA9IDMsCj4gKwkucXVpcmtzID0gUkNB Ul9MVkRTX1FVSVJLX0dFTjJfUExMQ1IgfCBSQ0FSX0xWRFNfUVVJUktfUEhZLAo+ICt9Owo+ICsK PiAgc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgcmNhcl9sdmRzX29mX3RhYmxlW10g PSB7Cj4gIAl7IC5jb21wYXRpYmxlID0gInJlbmVzYXMscjhhNzc0My1sdmRzIiwgLmRhdGEgPSAm cmNhcl9sdmRzX2dlbjJfaW5mbyB9LAo+ICAJeyAuY29tcGF0aWJsZSA9ICJyZW5lc2FzLHI4YTc3 OTAtbHZkcyIsIC5kYXRhID0gJnJjYXJfbHZkc19yOGE3NzkwX2luZm8gfSwKPiBAQCAtNTA2LDYg KzUyMiw3IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIHJjYXJfbHYKPiAgCXsg LmNvbXBhdGlibGUgPSAicmVuZXNhcyxyOGE3NzkzLWx2ZHMiLCAuZGF0YSA9ICZyY2FyX2x2ZHNf Z2VuMl9pbmZvIH0sCj4gIAl7IC5jb21wYXRpYmxlID0gInJlbmVzYXMscjhhNzc5NS1sdmRzIiwg LmRhdGEgPSAmcmNhcl9sdmRzX2dlbjNfaW5mbyB9LAo+ICAJeyAuY29tcGF0aWJsZSA9ICJyZW5l c2FzLHI4YTc3OTYtbHZkcyIsIC5kYXRhID0gJnJjYXJfbHZkc19nZW4zX2luZm8gfSwKPiArCXsg LmNvbXBhdGlibGUgPSAicmVuZXNhcyxyOGE3Nzk3MC1sdmRzIiwgLmRhdGEgPSAmcmNhcl9sdmRz X3I4YTc3OTcwX2luZm8KPiB9LCB7IH0KPiAgfTsKCi0tIApSZWdhcmRzLAoKTGF1cmVudCBQaW5j aGFydAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJp LWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==