From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:33790 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731235AbeISStR (ORCPT ); Wed, 19 Sep 2018 14:49:17 -0400 From: Laurent Pinchart To: Simon Horman Cc: Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Ulrich Hecht , Kieran Bingham Subject: Re: [PATCH v2 13/16] arm64: dts: renesas: r8a77990: Add display output support Date: Wed, 19 Sep 2018 16:11:36 +0300 Message-ID: <1942172.7Is2si9RQ9@avalon> In-Reply-To: <20180919083506.xuilcubl54q5djxr@verge.net.au> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <1591567.fSGLneYn9d@avalon> <20180919083506.xuilcubl54q5djxr@verge.net.au> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Simon, On Wednesday, 19 September 2018 11:35:07 EEST Simon Horman wrote: > On Mon, Sep 17, 2018 at 11:59:32AM +0300, Laurent Pinchart wrote: > > On Monday, 17 September 2018 11:54:04 EEST Laurent Pinchart wrote: > >> On Monday, 17 September 2018 11:47:15 EEST Laurent Pinchart wrote: > >>> On Monday, 17 September 2018 11:14:20 EEST Simon Horman wrote: > >>>> On Mon, Sep 17, 2018 at 09:50:55AM +0200, Simon Horman wrote: > >>>>> On Fri, Sep 14, 2018 at 12:10:43PM +0300, Laurent Pinchart wrote: > >>>>>> The R8A77990 (E3) platform has one RGB output and two LVDS > >>>>>> outputs connected to the DU. Add the DT nodes for the DU, LVDS > >>>>>> encoders and supporting VSP and FCP. > >>>>>> > >>>>>> Signed-off-by: Laurent Pinchart > >>>>>> > >>>>>> Tested-by: Jacopo Mondi > >>>>>> --- > >>>>>> > >>>>>> arch/arm64/boot/dts/renesas/r8a77990.dtsi | 167 ++++++++++++++++++++ > >>>>>> 1 file changed, 167 insertions(+) > >>>>>> > >>>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi > >>>>>> b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index > >>>>>> abb14af76c0e..600074ca3ee5 100644 > >>>>>> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi > >>>>>> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi [snip] > >>>>>> + lvds0: lvds-encoder@feb90000 { > >>>>>> + compatible = "renesas,r8a77990-lvds"; > >>>>>> + reg = <0 0xfeb90000 0 0x20>; > >>>>>> + clocks = <&cpg CPG_MOD 727>; > >>>>>> + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > >>>>>> + resets = <&cpg 727>; > >>>>>> + status = "disabled"; > >>>>>> + > >>>>>> + ports { > >>>>>> + #address-cells = <1>; > >>>>>> + #size-cells = <0>; > >>>>>> + > >>>>>> + port@0 { > >>>>>> + reg = <0>; > >>>>>> + lvds0_in: endpoint { > >>>>>> + remote-endpoint = <&du_out_lvds0>; > >>>>>> + }; > >>>>>> + }; > >>>>>> + > >>>>>> + port@1 { > >>>>>> + reg = <1>; > >>>>>> + lvds0_out: endpoint { > >>>>>> + }; > >>>>>> + }; > >>>>>> + }; > >>>>>> + }; > >>>>>> + > >>>>>> + lvds1: lvds-encoder@feb90100 { > >>>>>> + compatible = "renesas,r8a77990-lvds"; > >>>>>> + reg = <0 0xfeb90100 0 0x20>; > >>>>>> + clocks = <&cpg CPG_MOD 727>; > >>>>>> + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > >>>>>> + resets = <&cpg 726>; > >>>> > >>>> Also, is the missmatch between the index for the clock and reset > >>>> intentional? > >>> > >>> It is. According to the datasheet, the two LVDS encoders have > >>> different module stop bits, but share the same reset (lovely hardware > >>> design, it will be fun to support that in the driver :-S). > >> > >> Sorry, I got it wrong. it's bit 725 that is shared between the two LVDS > >> encoders, to reset the two LVDS PLLs together. The encoders themselves > >> still have independent reset bits. I'll fix this. > > > > And of course it's the clock you were commenting on, not the reset. *sigh* > > > > According to the datasheets the two LVDS encoders share one MSTP. Whether > > that's a mistake in the documentation or not I can't tell yet, as I have > > only tested LVDS0. > > Could we follow-up with the HW team? > I'm not opposed to taking the patch with this portion as-is > but it would be good to clarify this somehow. I tried setting the clock to MSTP 726, and I then get vblank interrupt timeouts. Furthermore I've now tested the LVDS1 output with a display panel, and while I still can't get the backlight to work, the panel displays the correct image with MSTP 727. I thus conclude that the above is correct. > >>>>>> + status = "disabled"; > >>>>>> + > >>>>>> + ports { > >>>>>> + #address-cells = <1>; > >>>>>> + #size-cells = <0>; > >>>>>> + > >>>>>> + port@0 { > >>>>>> + reg = <0>; > >>>>>> + lvds1_in: endpoint { > >>>>>> + remote-endpoint = <&du_out_lvds1>; > >>>>>> + }; > >>>>>> + }; > >>>>>> + > >>>>>> + port@1 { > >>>>>> + reg = <1>; > >>>>>> + lvds1_out: endpoint { > >>>>>> + }; > >>>>>> + }; > >>>>>> + }; > >>>>>> + }; -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH v2 13/16] arm64: dts: renesas: r8a77990: Add display output support Date: Wed, 19 Sep 2018 16:11:36 +0300 Message-ID: <1942172.7Is2si9RQ9@avalon> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <1591567.fSGLneYn9d@avalon> <20180919083506.xuilcubl54q5djxr@verge.net.au> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 149AD6E255 for ; Wed, 19 Sep 2018 13:11:24 +0000 (UTC) In-Reply-To: <20180919083506.xuilcubl54q5djxr@verge.net.au> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Simon Horman Cc: linux-renesas-soc@vger.kernel.org, Ulrich Hecht , Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org SGkgU2ltb24sCgpPbiBXZWRuZXNkYXksIDE5IFNlcHRlbWJlciAyMDE4IDExOjM1OjA3IEVFU1Qg U2ltb24gSG9ybWFuIHdyb3RlOgo+IE9uIE1vbiwgU2VwIDE3LCAyMDE4IGF0IDExOjU5OjMyQU0g KzAzMDAsIExhdXJlbnQgUGluY2hhcnQgd3JvdGU6Cj4gPiBPbiBNb25kYXksIDE3IFNlcHRlbWJl ciAyMDE4IDExOjU0OjA0IEVFU1QgTGF1cmVudCBQaW5jaGFydCB3cm90ZToKPiA+PiBPbiBNb25k YXksIDE3IFNlcHRlbWJlciAyMDE4IDExOjQ3OjE1IEVFU1QgTGF1cmVudCBQaW5jaGFydCB3cm90 ZToKPiA+Pj4gT24gTW9uZGF5LCAxNyBTZXB0ZW1iZXIgMjAxOCAxMToxNDoyMCBFRVNUIFNpbW9u IEhvcm1hbiB3cm90ZToKPiA+Pj4+IE9uIE1vbiwgU2VwIDE3LCAyMDE4IGF0IDA5OjUwOjU1QU0g KzAyMDAsIFNpbW9uIEhvcm1hbiB3cm90ZToKPiA+Pj4+PiBPbiBGcmksIFNlcCAxNCwgMjAxOCBh dCAxMjoxMDo0M1BNICswMzAwLCBMYXVyZW50IFBpbmNoYXJ0IHdyb3RlOgo+ID4+Pj4+PiBUaGUg UjhBNzc5OTAgKEUzKSBwbGF0Zm9ybSBoYXMgb25lIFJHQiBvdXRwdXQgYW5kIHR3byBMVkRTCj4g Pj4+Pj4+IG91dHB1dHMgY29ubmVjdGVkIHRvIHRoZSBEVS4gQWRkIHRoZSBEVCBub2RlcyBmb3Ig dGhlIERVLCBMVkRTCj4gPj4+Pj4+IGVuY29kZXJzIGFuZCBzdXBwb3J0aW5nIFZTUCBhbmQgRkNQ Lgo+ID4+Pj4+PiAKPiA+Pj4+Pj4gU2lnbmVkLW9mZi1ieTogTGF1cmVudCBQaW5jaGFydAo+ID4+ Pj4+PiA8bGF1cmVudC5waW5jaGFydCtyZW5lc2FzQGlkZWFzb25ib2FyZC5jb20+Cj4gPj4+Pj4+ IFRlc3RlZC1ieTogSmFjb3BvIE1vbmRpIDxqYWNvcG8rcmVuZXNhc0BqbW9uZGkub3JnPgo+ID4+ Pj4+PiAtLS0KPiA+Pj4+Pj4gCj4gPj4+Pj4+ICBhcmNoL2FybTY0L2Jvb3QvZHRzL3JlbmVzYXMv cjhhNzc5OTAuZHRzaSB8IDE2NyArKysrKysrKysrKysrKysrKysrKwo+ID4+Pj4+PiAgMSBmaWxl IGNoYW5nZWQsIDE2NyBpbnNlcnRpb25zKCspCj4gPj4+Pj4+IAo+ID4+Pj4+PiBkaWZmIC0tZ2l0 IGEvYXJjaC9hcm02NC9ib290L2R0cy9yZW5lc2FzL3I4YTc3OTkwLmR0c2kKPiA+Pj4+Pj4gYi9h cmNoL2FybTY0L2Jvb3QvZHRzL3JlbmVzYXMvcjhhNzc5OTAuZHRzaSBpbmRleAo+ID4+Pj4+PiBh YmIxNGFmNzZjMGUuLjYwMDA3NGNhM2VlNSAxMDA2NDQKPiA+Pj4+Pj4gLS0tIGEvYXJjaC9hcm02 NC9ib290L2R0cy9yZW5lc2FzL3I4YTc3OTkwLmR0c2kKPiA+Pj4+Pj4gKysrIGIvYXJjaC9hcm02 NC9ib290L2R0cy9yZW5lc2FzL3I4YTc3OTkwLmR0c2kKCltzbmlwXQoKPiA+Pj4+Pj4gKwkJbHZk czA6IGx2ZHMtZW5jb2RlckBmZWI5MDAwMCB7Cj4gPj4+Pj4+ICsJCQljb21wYXRpYmxlID0gInJl bmVzYXMscjhhNzc5OTAtbHZkcyI7Cj4gPj4+Pj4+ICsJCQlyZWcgPSA8MCAweGZlYjkwMDAwIDAg MHgyMD47Cj4gPj4+Pj4+ICsJCQljbG9ja3MgPSA8JmNwZyBDUEdfTU9EIDcyNz47Cj4gPj4+Pj4+ ICsJCQlwb3dlci1kb21haW5zID0gPCZzeXNjIFI4QTc3OTkwX1BEX0FMV0FZU19PTj47Cj4gPj4+ Pj4+ICsJCQlyZXNldHMgPSA8JmNwZyA3Mjc+Owo+ID4+Pj4+PiArCQkJc3RhdHVzID0gImRpc2Fi bGVkIjsKPiA+Pj4+Pj4gKwo+ID4+Pj4+PiArCQkJcG9ydHMgewo+ID4+Pj4+PiArCQkJCSNhZGRy ZXNzLWNlbGxzID0gPDE+Owo+ID4+Pj4+PiArCQkJCSNzaXplLWNlbGxzID0gPDA+Owo+ID4+Pj4+ PiArCj4gPj4+Pj4+ICsJCQkJcG9ydEAwIHsKPiA+Pj4+Pj4gKwkJCQkJcmVnID0gPDA+Owo+ID4+ Pj4+PiArCQkJCQlsdmRzMF9pbjogZW5kcG9pbnQgewo+ID4+Pj4+PiArCQkJCQkJcmVtb3RlLWVu ZHBvaW50ID0gPCZkdV9vdXRfbHZkczA+Owo+ID4+Pj4+PiArCQkJCQl9Owo+ID4+Pj4+PiArCQkJ CX07Cj4gPj4+Pj4+ICsKPiA+Pj4+Pj4gKwkJCQlwb3J0QDEgewo+ID4+Pj4+PiArCQkJCQlyZWcg PSA8MT47Cj4gPj4+Pj4+ICsJCQkJCWx2ZHMwX291dDogZW5kcG9pbnQgewo+ID4+Pj4+PiArCQkJ CQl9Owo+ID4+Pj4+PiArCQkJCX07Cj4gPj4+Pj4+ICsJCQl9Owo+ID4+Pj4+PiArCQl9Owo+ID4+ Pj4+PiArCj4gPj4+Pj4+ICsJCWx2ZHMxOiBsdmRzLWVuY29kZXJAZmViOTAxMDAgewo+ID4+Pj4+ PiArCQkJY29tcGF0aWJsZSA9ICJyZW5lc2FzLHI4YTc3OTkwLWx2ZHMiOwo+ID4+Pj4+PiArCQkJ cmVnID0gPDAgMHhmZWI5MDEwMCAwIDB4MjA+Owo+ID4+Pj4+PiArCQkJY2xvY2tzID0gPCZjcGcg Q1BHX01PRCA3Mjc+Owo+ID4+Pj4+PiArCQkJcG93ZXItZG9tYWlucyA9IDwmc3lzYyBSOEE3Nzk5 MF9QRF9BTFdBWVNfT04+Owo+ID4+Pj4+PiArCQkJcmVzZXRzID0gPCZjcGcgNzI2PjsKPiA+Pj4+ IAo+ID4+Pj4gQWxzbywgaXMgdGhlIG1pc3NtYXRjaCBiZXR3ZWVuIHRoZSBpbmRleCBmb3IgdGhl IGNsb2NrIGFuZCByZXNldAo+ID4+Pj4gaW50ZW50aW9uYWw/Cj4gPj4+IAo+ID4+PiBJdCBpcy4g QWNjb3JkaW5nIHRvIHRoZSBkYXRhc2hlZXQsIHRoZSB0d28gTFZEUyBlbmNvZGVycyBoYXZlCj4g Pj4+IGRpZmZlcmVudCBtb2R1bGUgc3RvcCBiaXRzLCBidXQgc2hhcmUgdGhlIHNhbWUgcmVzZXQg KGxvdmVseSBoYXJkd2FyZQo+ID4+PiBkZXNpZ24sIGl0IHdpbGwgYmUgZnVuIHRvIHN1cHBvcnQg dGhhdCBpbiB0aGUgZHJpdmVyIDotUykuCj4gPj4gCj4gPj4gU29ycnksIEkgZ290IGl0IHdyb25n LiBpdCdzIGJpdCA3MjUgdGhhdCBpcyBzaGFyZWQgYmV0d2VlbiB0aGUgdHdvIExWRFMKPiA+PiBl bmNvZGVycywgdG8gcmVzZXQgdGhlIHR3byBMVkRTIFBMTHMgdG9nZXRoZXIuIFRoZSBlbmNvZGVy cyB0aGVtc2VsdmVzCj4gPj4gc3RpbGwgaGF2ZSBpbmRlcGVuZGVudCByZXNldCBiaXRzLiBJJ2xs IGZpeCB0aGlzLgo+ID4gCj4gPiBBbmQgb2YgY291cnNlIGl0J3MgdGhlIGNsb2NrIHlvdSB3ZXJl IGNvbW1lbnRpbmcgb24sIG5vdCB0aGUgcmVzZXQuICpzaWdoKgo+ID4gCj4gPiBBY2NvcmRpbmcg dG8gdGhlIGRhdGFzaGVldHMgdGhlIHR3byBMVkRTIGVuY29kZXJzIHNoYXJlIG9uZSBNU1RQLiBX aGV0aGVyCj4gPiB0aGF0J3MgYSBtaXN0YWtlIGluIHRoZSBkb2N1bWVudGF0aW9uIG9yIG5vdCBJ IGNhbid0IHRlbGwgeWV0LCBhcyBJIGhhdmUKPiA+IG9ubHkgdGVzdGVkIExWRFMwLgo+IAo+IENv dWxkIHdlIGZvbGxvdy11cCB3aXRoIHRoZSBIVyB0ZWFtPwo+IEknbSBub3Qgb3Bwb3NlZCB0byB0 YWtpbmcgdGhlIHBhdGNoIHdpdGggdGhpcyBwb3J0aW9uIGFzLWlzCj4gYnV0IGl0IHdvdWxkIGJl IGdvb2QgdG8gY2xhcmlmeSB0aGlzIHNvbWVob3cuCgpJIHRyaWVkIHNldHRpbmcgdGhlIGNsb2Nr IHRvIE1TVFAgNzI2LCBhbmQgSSB0aGVuIGdldCB2YmxhbmsgaW50ZXJydXB0IAp0aW1lb3V0cy4g RnVydGhlcm1vcmUgSSd2ZSBub3cgdGVzdGVkIHRoZSBMVkRTMSBvdXRwdXQgd2l0aCBhIGRpc3Bs YXkgcGFuZWwsIAphbmQgd2hpbGUgSSBzdGlsbCBjYW4ndCBnZXQgdGhlIGJhY2tsaWdodCB0byB3 b3JrLCB0aGUgcGFuZWwgZGlzcGxheXMgdGhlIApjb3JyZWN0IGltYWdlIHdpdGggTVNUUCA3Mjcu IEkgdGh1cyBjb25jbHVkZSB0aGF0IHRoZSBhYm92ZSBpcyBjb3JyZWN0LgoKPiA+Pj4+Pj4gKwkJ CXN0YXR1cyA9ICJkaXNhYmxlZCI7Cj4gPj4+Pj4+ICsKPiA+Pj4+Pj4gKwkJCXBvcnRzIHsKPiA+ Pj4+Pj4gKwkJCQkjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+Pj4+Pj4gKwkJCQkjc2l6ZS1jZWxs cyA9IDwwPjsKPiA+Pj4+Pj4gKwo+ID4+Pj4+PiArCQkJCXBvcnRAMCB7Cj4gPj4+Pj4+ICsJCQkJ CXJlZyA9IDwwPjsKPiA+Pj4+Pj4gKwkJCQkJbHZkczFfaW46IGVuZHBvaW50IHsKPiA+Pj4+Pj4g KwkJCQkJCXJlbW90ZS1lbmRwb2ludCA9IDwmZHVfb3V0X2x2ZHMxPjsKPiA+Pj4+Pj4gKwkJCQkJ fTsKPiA+Pj4+Pj4gKwkJCQl9Owo+ID4+Pj4+PiArCj4gPj4+Pj4+ICsJCQkJcG9ydEAxIHsKPiA+ Pj4+Pj4gKwkJCQkJcmVnID0gPDE+Owo+ID4+Pj4+PiArCQkJCQlsdmRzMV9vdXQ6IGVuZHBvaW50 IHsKPiA+Pj4+Pj4gKwkJCQkJfTsKPiA+Pj4+Pj4gKwkJCQl9Owo+ID4+Pj4+PiArCQkJfTsKPiA+ Pj4+Pj4gKwkJfTsKCi0tIApSZWdhcmRzLAoKTGF1cmVudCBQaW5jaGFydAoKCgpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBs aXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVz a3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK