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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Freitag, 23. Juni 2023, 05:06:44 CEST schrieb Stefan O'Rear: > On Thu, Jun 22, 2023, at 4:35 PM, Heiko Stübner wrote: > > Am Donnerstag, 22. Juni 2023, 20:58:37 CEST schrieb Stefan O'Rear: > >> Are you aware of "3.7. Vector Fixed-Point Fields in fcsr" in > >> riscv-v-spec-0.7.1.pdf? > > > > oh wow, thanks a lot for that pointer, now I understand your concern. > > > > So in vector-0.7.1 fcsr[10:9] mirrors vxrm and fcsr[8] mirrors vxsat. > > > > > > On a positive note, the T-Head cores seem to not implement the full > > vector 0.7.1 specification after all, in the documentation I have [0] > > fcsr[31:8] are declared as "0" and uppermost bits are [7:5] for the "frm" > > field. > > Given that the pdf you linked does not mention any vector CSRs, I am not > confident that it provides a complete and accurate description of vector > functionality in other registers for the C906 with vector extension. > > Assuming that you have access to such a chip, I would be much happier with > the proposed "just a comment" approach if our understanding of the behavior > were confirmed on hardware (specifically: csr_write(CSR_FCSR, 0x700) should > not affect csr_read(CSR_VXRM) or csr_read(CSR_VXSAT)). For one, you're right that I should definitly try to confirm this on hardware :-) . But also the VXSAT and VXRM CSRs are actually documented in that pdf on page 335 Heiko > > -s > > > So I guess a code comment should suffice to explain :-) > > > > > > Regards > > Heiko > > > > > > [0] > > https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf > > 16.3.1.3 浮点控制状态寄存器（FCSR） on page 334 >