diff for duplicates of <1978482.7WNnERYOPX@diego> diff --git a/a/1.txt b/N1/1.txt index 948ea41..ca3d103 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,16 +1,15 @@ Hi Xing, -Am Mittwoch, 9. M=E4rz 2016, 10:37:04 schrieb Xing Zheng: +Am Mittwoch, 9. März 2016, 10:37:04 schrieb Xing Zheng: > There are need to support Multi-CRUs probability in future, but > it is not supported on the current Rockchip Clock Framework. ->=20 +> > Therefore, this patch add support a provider as the parameter > handler when we call the clock register functions for per CRU. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> -I've applied that in a clk branch for 4.7 [0] with some changes detaile= -d +I've applied that in a clk branch for 4.7 [0] with some changes detailed below. If you can, please check that I didn't mess anything up :-) I've sucessfully booted that on both a rk3036 and rk3288 as well. @@ -18,16 +17,14 @@ I've sucessfully booted that on both a rk3036 and rk3288 as well. Heiko -[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g= -it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f= -864 +[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=d509ddf2e57c99ae760d1a289b85f1e0d729f864 > --- ->=20 +> > Changes in v3: None > Changes in v2: None ->=20 +> > drivers/clk/rockchip/clk-pll.c | 30 ++++---- > drivers/clk/rockchip/clk-rk3036.c | 17 +++-- > drivers/clk/rockchip/clk-rk3188.c | 48 ++++++++---- @@ -35,8 +32,7 @@ it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f= > drivers/clk/rockchip/clk-rk3288.c | 19 +++-- > drivers/clk/rockchip/clk-rk3368.c | 21 ++++-- > drivers/clk/rockchip/clk.c | 148 -> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h = - | =20 +> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h | > 49 ++++++++---- > 8 files changed, 231 insertions(+), 118 deletions(-) @@ -45,122 +41,115 @@ it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f= > diff --git a/drivers/clk/rockchip/clk-rk3188.c > b/drivers/clk/rockchip/clk-rk3188.c index e832403..7c73c51 100644 > --- a/drivers/clk/rockchip/clk-rk3188.c -> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks= -[] -> __initconst =3D { "hclk_cpubus" +> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks[] +> __initconst = { "hclk_cpubus" > }; ->=20 +> > -static void __init rk3188_common_clk_init(struct device_node *np) -> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(s= -truct +> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct > device_node *np) { -> +=09struct rockchip_clk_provider *ctx; -> =09void __iomem *reg_base; ->=20 -> =09reg_base =3D of_iomap(np, 0); -> =09if (!reg_base) { -> =09=09pr_err("%s: could not map cru region\n", __func__); -> -=09=09return; -> +=09=09return ERR_PTR(-ENOMEM); -> =09} ->=20 -> -=09rockchip_clk_init(np, reg_base, CLK_NR_CLKS); -> +=09ctx =3D rockchip_clk_init(np, reg_base, CLK_NR_CLKS); -> +=09if (IS_ERR(ctx)) { -> +=09=09pr_err("%s: rockchip clk init failed\n", __func__); -> +=09=09return ERR_PTR(-ENOMEM); -> +=09} ->=20 -> -=09rockchip_clk_register_branches(common_clk_branches, -> +=09rockchip_clk_register_branches(ctx, common_clk_branches, -> =09=09=09=09 ARRAY_SIZE(common_clk_branches)); ->=20 -> =09rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0)= -, -> =09=09=09=09 ROCKCHIP_SOFTRST_HIWORD_MASK); ->=20 -> -=09rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL); -> +=09rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL= -); +> + struct rockchip_clk_provider *ctx; +> void __iomem *reg_base; +> +> reg_base = of_iomap(np, 0); +> if (!reg_base) { +> pr_err("%s: could not map cru region\n", __func__); +> - return; +> + return ERR_PTR(-ENOMEM); +> } +> +> - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); +> + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); +> + if (IS_ERR(ctx)) { +> + pr_err("%s: rockchip clk init failed\n", __func__); +> + return ERR_PTR(-ENOMEM); +> + } +> +> - rockchip_clk_register_branches(common_clk_branches, +> + rockchip_clk_register_branches(ctx, common_clk_branches, +> ARRAY_SIZE(common_clk_branches)); +> +> rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), +> ROCKCHIP_SOFTRST_HIWORD_MASK); +> +> - rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL); +> + rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); > + -> +=09return ctx; +> + return ctx; > } ->=20 +> > static void __init rk3066a_clk_init(struct device_node *np) > { -> -=09rk3188_common_clk_init(np); -> -=09rockchip_clk_register_plls(rk3066_pll_clks, -> +=09struct rockchip_clk_provider *ctx; +> - rk3188_common_clk_init(np); +> - rockchip_clk_register_plls(rk3066_pll_clks, +> + struct rockchip_clk_provider *ctx; > + -> +=09ctx =3D rk3188_common_clk_init(np); -> +=09if (IS_ERR(ctx)) { -> +=09=09pr_err("%s: common clk init failed\n", __func__); -> +=09=09return; -> +=09} +> + ctx = rk3188_common_clk_init(np); +> + if (IS_ERR(ctx)) { +> + pr_err("%s: common clk init failed\n", __func__); +> + return; +> + } I've dropped the pr_err + parentheses, as rk3188_common_clk_init will already output a suitable error. > + -> +=09rockchip_clk_register_plls(ctx, rk3066_pll_clks, -> =09=09=09=09 ARRAY_SIZE(rk3066_pll_clks), -> =09=09=09=09 RK3066_GRF_SOC_STATUS); -> -=09rockchip_clk_register_branches(rk3066a_clk_branches, -> +=09rockchip_clk_register_branches(ctx, rk3066a_clk_branches, -> =09=09=09=09 ARRAY_SIZE(rk3066a_clk_branches)); -> -=09rockchip_clk_register_armclk(ARMCLK, "armclk", -> +=09rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", -> =09=09=09mux_armclk_p, ARRAY_SIZE(mux_armclk_p), -> =09=09=09&rk3066_cpuclk_data, rk3066_cpuclk_rates, -> =09=09=09ARRAY_SIZE(rk3066_cpuclk_rates)); -> =09rockchip_clk_protect_critical(rk3188_critical_clocks, -> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks)); -> +=09rockchip_clk_of_add_provider(np, ctx); +> + rockchip_clk_register_plls(ctx, rk3066_pll_clks, +> ARRAY_SIZE(rk3066_pll_clks), +> RK3066_GRF_SOC_STATUS); +> - rockchip_clk_register_branches(rk3066a_clk_branches, +> + rockchip_clk_register_branches(ctx, rk3066a_clk_branches, +> ARRAY_SIZE(rk3066a_clk_branches)); +> - rockchip_clk_register_armclk(ARMCLK, "armclk", +> + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", +> mux_armclk_p, ARRAY_SIZE(mux_armclk_p), +> &rk3066_cpuclk_data, rk3066_cpuclk_rates, +> ARRAY_SIZE(rk3066_cpuclk_rates)); +> rockchip_clk_protect_critical(rk3188_critical_clocks, +> ARRAY_SIZE(rk3188_critical_clocks)); +> + rockchip_clk_of_add_provider(np, ctx); > } -> CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init= -); ->=20 +> CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); +> > static void __init rk3188a_clk_init(struct device_node *np) > { -> +=09struct rockchip_clk_provider *ctx; -> =09struct clk *clk1, *clk2; -> =09unsigned long rate; -> =09int ret; ->=20 -> -=09rk3188_common_clk_init(np); -> -=09rockchip_clk_register_plls(rk3188_pll_clks, -> +=09ctx =3D rk3188_common_clk_init(np); -> +=09if (IS_ERR(ctx)) { -> +=09=09pr_err("%s: common clk init failed\n", __func__); -> +=09=09return; -> +=09} +> + struct rockchip_clk_provider *ctx; +> struct clk *clk1, *clk2; +> unsigned long rate; +> int ret; +> +> - rk3188_common_clk_init(np); +> - rockchip_clk_register_plls(rk3188_pll_clks, +> + ctx = rk3188_common_clk_init(np); +> + if (IS_ERR(ctx)) { +> + pr_err("%s: common clk init failed\n", __func__); +> + return; +> + } same as above > + -> +=09rockchip_clk_register_plls(ctx, rk3188_pll_clks, -> =09=09=09=09 ARRAY_SIZE(rk3188_pll_clks), -> =09=09=09=09 RK3188_GRF_SOC_STATUS); -> -=09rockchip_clk_register_branches(rk3188_clk_branches, -> +=09rockchip_clk_register_branches(ctx, rk3188_clk_branches, -> =09=09=09=09 ARRAY_SIZE(rk3188_clk_branches)); -> -=09rockchip_clk_register_armclk(ARMCLK, "armclk", -> +=09rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", -> =09=09=09=09 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), -> =09=09=09=09 &rk3188_cpuclk_data, rk3188_cpuclk_rates, -> =09=09=09=09 ARRAY_SIZE(rk3188_cpuclk_rates)); -> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device= -_node +> + rockchip_clk_register_plls(ctx, rk3188_pll_clks, +> ARRAY_SIZE(rk3188_pll_clks), +> RK3188_GRF_SOC_STATUS); +> - rockchip_clk_register_branches(rk3188_clk_branches, +> + rockchip_clk_register_branches(ctx, rk3188_clk_branches, +> ARRAY_SIZE(rk3188_clk_branches)); +> - rockchip_clk_register_armclk(ARMCLK, "armclk", +> + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", +> mux_armclk_p, ARRAY_SIZE(mux_armclk_p), +> &rk3188_cpuclk_data, rk3188_cpuclk_rates, +> ARRAY_SIZE(rk3188_cpuclk_rates)); +> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device_node > *np) ->=20 -> =09rockchip_clk_protect_critical(rk3188_critical_clocks, -> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks)); -> +=09rockchip_clk_of_add_provider(np, ctx); +> +> rockchip_clk_protect_critical(rk3188_critical_clocks, +> ARRAY_SIZE(rk3188_critical_clocks)); +> + rockchip_clk_of_add_provider(np, ctx); > } -> CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init= -); +> CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); [...] @@ -171,7 +160,7 @@ _node > @@ -312,66 +316,94 @@ static struct clk > *rockchip_clk_register_factor_branch(const char *name, return clk; > } ->=20 +> > -static DEFINE_SPINLOCK(clk_lock); > -static struct clk **clk_table; > -static void __iomem *reg_base; @@ -179,109 +168,100 @@ _node > -static struct device_node *cru_node; > -static struct regmap *grf; > - -> -void __init rockchip_clk_init(struct device_node *np, void __iomem *= -base, -> -=09=09=09 unsigned long nr_clks) -> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device= -_node +> -void __init rockchip_clk_init(struct device_node *np, void __iomem *base, +> - unsigned long nr_clks) +> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device_node I've added a space between the asterisk and __init flag -> *np, +=09=09=09void __iomem *base, unsigned long nr_clks) +> *np, + void __iomem *base, unsigned long nr_clks) > { -> -=09reg_base =3D base; -> -=09cru_node =3D np; -> -=09grf =3D ERR_PTR(-EPROBE_DEFER); -> +=09struct rockchip_clk_provider *ctx; -> +=09struct clk **clk_table; -> +=09int i; +> - reg_base = base; +> - cru_node = np; +> - grf = ERR_PTR(-EPROBE_DEFER); +> + struct rockchip_clk_provider *ctx; +> + struct clk **clk_table; +> + int i; > + -> +=09ctx =3D kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL)= -; -> +=09if (!ctx) { -> +=09=09pr_err("%s: Could not allocate clock provider context\n", -> +=09=09=09__func__); -> +=09=09return ERR_PTR(-ENOMEM); -> +=09} ->=20 -> =09clk_table =3D kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);= - -> -=09if (!clk_table) -> -=09=09pr_err("%s: could not allocate clock lookup table\n", __func__= -); -> +=09if (!clk_table) { -> +=09=09pr_err("%s: Could not allocate clock lookup table\n", -> +=09=09=09__func__); -> +=09=09goto err_free; -> +=09} +> + ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); +> + if (!ctx) { +> + pr_err("%s: Could not allocate clock provider context\n", +> + __func__); +> + return ERR_PTR(-ENOMEM); +> + } +> +> clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); +> - if (!clk_table) +> - pr_err("%s: could not allocate clock lookup table\n", __func__); +> + if (!clk_table) { +> + pr_err("%s: Could not allocate clock lookup table\n", +> + __func__); +> + goto err_free; +> + } > + -> +=09for (i =3D 0; i < nr_clks; ++i) -> +=09=09clk_table[i] =3D ERR_PTR(-ENOENT); ->=20 -> -=09clk_data.clks =3D clk_table; -> -=09clk_data.clk_num =3D nr_clks; -> -=09of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -> +=09ctx->reg_base =3D base; -> +=09ctx->clk_data.clks =3D clk_table; -> +=09ctx->clk_data.clk_num =3D nr_clks; -> +=09ctx->cru_node =3D np; -> +=09ctx->grf =3D ERR_PTR(-EPROBE_DEFER); -> +=09spin_lock_init(&ctx->lock); +> + for (i = 0; i < nr_clks; ++i) +> + clk_table[i] = ERR_PTR(-ENOENT); +> +> - clk_data.clks = clk_table; +> - clk_data.clk_num = nr_clks; +> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +> + ctx->reg_base = base; +> + ctx->clk_data.clks = clk_table; +> + ctx->clk_data.clk_num = nr_clks; +> + ctx->cru_node = np; +> + ctx->grf = ERR_PTR(-EPROBE_DEFER); +> + spin_lock_init(&ctx->lock); > + -> +=09return ctx; +> + return ctx; > + > +err_free: -> +=09kfree(ctx); -> +=09return ERR_PTR(-ENOMEM); +> + kfree(ctx); +> + return ERR_PTR(-ENOMEM); > +} > + > +void __init rockchip_clk_of_add_provider(struct device_node *np, -> +=09=09=09=09struct rockchip_clk_provider *ctx) +> + struct rockchip_clk_provider *ctx) > +{ -> +=09if (np) { -> +=09=09if (of_clk_add_provider(np, of_clk_src_onecell_get, -> +=09=09=09=09=09&ctx->clk_data)) -> +=09=09=09panic("could not register clk provider\n"); +> + if (np) { +> + if (of_clk_add_provider(np, of_clk_src_onecell_get, +> + &ctx->clk_data)) +> + panic("could not register clk provider\n"); -I've changed that to a pr_err, again no need to panic on this, as letti= -ng -the kernel run may give the affected developer more hints what may be w= -rong. +I've changed that to a pr_err, again no need to panic on this, as letting +the kernel run may give the affected developer more hints what may be wrong. -> +=09} +> + } > } ->=20 +> > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index 7aafe18..b7affb6 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -127,6 +128,20 @@ enum rockchip_pll_type { -> =09.nb =3D _nb,=09=09=09=09=09=09\ +> .nb = _nb, \ > } ->=20 +> > +/** > + * struct rockchip_clk_provider: information about clock provider > + * @reg_base: virtual address for the register base. -> + * @clk_data: holds clock related data like clk* and number of clock= -s. -> + * @lock: maintains exclusion between callbacks for a given clock-pr= -ovider. +> + * @clk_data: holds clock related data like clk* and number of clocks. +> + * @lock: maintains exclusion between callbacks for a given clock-provider. I've added the missing kerneldoc entries here > + */ > +struct rockchip_clk_provider { -> +=09void __iomem *reg_base; -> +=09struct clk_onecell_data clk_data; -> +=09struct device_node *cru_node; -> +=09struct regmap *grf; -> +=09spinlock_t lock; +> + void __iomem *reg_base; +> + struct clk_onecell_data clk_data; +> + struct device_node *cru_node; +> + struct regmap *grf; +> + spinlock_t lock; > +}; > + > struct rockchip_pll_rate_table { -> =09unsigned long rate; -> =09unsigned int nr; +> unsigned long rate; +> unsigned int nr; diff --git a/a/content_digest b/N1/content_digest index 35e221b..0a2fbda 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -18,17 +18,16 @@ "b\0" "Hi Xing,\n" "\n" - "Am Mittwoch, 9. M=E4rz 2016, 10:37:04 schrieb Xing Zheng:\n" + "Am Mittwoch, 9. M\303\244rz 2016, 10:37:04 schrieb Xing Zheng:\n" "> There are need to support Multi-CRUs probability in future, but\n" "> it is not supported on the current Rockchip Clock Framework.\n" - ">=20\n" + "> \n" "> Therefore, this patch add support a provider as the parameter\n" "> handler when we call the clock register functions for per CRU.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" - "I've applied that in a clk branch for 4.7 [0] with some changes detaile=\n" - "d\n" + "I've applied that in a clk branch for 4.7 [0] with some changes detailed\n" "below. If you can, please check that I didn't mess anything up :-)\n" "\n" "I've sucessfully booted that on both a rk3036 and rk3288 as well.\n" @@ -36,16 +35,14 @@ "\n" "Heiko\n" "\n" - "[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g=\n" - "it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f=\n" - "864\n" + "[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=d509ddf2e57c99ae760d1a289b85f1e0d729f864\n" "\n" "\n" "> ---\n" - ">=20\n" + "> \n" "> Changes in v3: None\n" "> Changes in v2: None\n" - ">=20\n" + "> \n" "> drivers/clk/rockchip/clk-pll.c | 30 ++++----\n" "> drivers/clk/rockchip/clk-rk3036.c | 17 +++--\n" "> drivers/clk/rockchip/clk-rk3188.c | 48 ++++++++----\n" @@ -53,8 +50,7 @@ "> drivers/clk/rockchip/clk-rk3288.c | 19 +++--\n" "> drivers/clk/rockchip/clk-rk3368.c | 21 ++++--\n" "> drivers/clk/rockchip/clk.c | 148\n" - "> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h =\n" - " | =20\n" + "> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h | \n" "> 49 ++++++++----\n" "> 8 files changed, 231 insertions(+), 118 deletions(-)\n" "\n" @@ -63,122 +59,115 @@ "> diff --git a/drivers/clk/rockchip/clk-rk3188.c\n" "> b/drivers/clk/rockchip/clk-rk3188.c index e832403..7c73c51 100644\n" "> --- a/drivers/clk/rockchip/clk-rk3188.c\n" - "> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks=\n" - "[]\n" - "> __initconst =3D { \"hclk_cpubus\"\n" + "> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks[]\n" + "> __initconst = { \"hclk_cpubus\"\n" "> };\n" - ">=20\n" + "> \n" "> -static void __init rk3188_common_clk_init(struct device_node *np)\n" - "> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(s=\n" - "truct\n" + "> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct\n" "> device_node *np) {\n" - "> +=09struct rockchip_clk_provider *ctx;\n" - "> =09void __iomem *reg_base;\n" - ">=20\n" - "> =09reg_base =3D of_iomap(np, 0);\n" - "> =09if (!reg_base) {\n" - "> =09=09pr_err(\"%s: could not map cru region\\n\", __func__);\n" - "> -=09=09return;\n" - "> +=09=09return ERR_PTR(-ENOMEM);\n" - "> =09}\n" - ">=20\n" - "> -=09rockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" - "> +=09ctx =3D rockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" - "> +=09if (IS_ERR(ctx)) {\n" - "> +=09=09pr_err(\"%s: rockchip clk init failed\\n\", __func__);\n" - "> +=09=09return ERR_PTR(-ENOMEM);\n" - "> +=09}\n" - ">=20\n" - "> -=09rockchip_clk_register_branches(common_clk_branches,\n" - "> +=09rockchip_clk_register_branches(ctx, common_clk_branches,\n" - "> =09=09=09=09 ARRAY_SIZE(common_clk_branches));\n" - ">=20\n" - "> =09rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0)=\n" - ",\n" - "> =09=09=09=09 ROCKCHIP_SOFTRST_HIWORD_MASK);\n" - ">=20\n" - "> -=09rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);\n" - "> +=09rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL=\n" - ");\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" + "> \tvoid __iomem *reg_base;\n" + "> \n" + "> \treg_base = of_iomap(np, 0);\n" + "> \tif (!reg_base) {\n" + "> \t\tpr_err(\"%s: could not map cru region\\n\", __func__);\n" + "> -\t\treturn;\n" + "> +\t\treturn ERR_PTR(-ENOMEM);\n" + "> \t}\n" + "> \n" + "> -\trockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" + "> +\tctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" + "> +\tif (IS_ERR(ctx)) {\n" + "> +\t\tpr_err(\"%s: rockchip clk init failed\\n\", __func__);\n" + "> +\t\treturn ERR_PTR(-ENOMEM);\n" + "> +\t}\n" + "> \n" + "> -\trockchip_clk_register_branches(common_clk_branches,\n" + "> +\trockchip_clk_register_branches(ctx, common_clk_branches,\n" + "> \t\t\t\t ARRAY_SIZE(common_clk_branches));\n" + "> \n" + "> \trockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),\n" + "> \t\t\t\t ROCKCHIP_SOFTRST_HIWORD_MASK);\n" + "> \n" + "> -\trockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);\n" + "> +\trockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);\n" "> +\n" - "> +=09return ctx;\n" + "> +\treturn ctx;\n" "> }\n" - ">=20\n" + "> \n" "> static void __init rk3066a_clk_init(struct device_node *np)\n" "> {\n" - "> -=09rk3188_common_clk_init(np);\n" - "> -=09rockchip_clk_register_plls(rk3066_pll_clks,\n" - "> +=09struct rockchip_clk_provider *ctx;\n" + "> -\trk3188_common_clk_init(np);\n" + "> -\trockchip_clk_register_plls(rk3066_pll_clks,\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" "> +\n" - "> +=09ctx =3D rk3188_common_clk_init(np);\n" - "> +=09if (IS_ERR(ctx)) {\n" - "> +=09=09pr_err(\"%s: common clk init failed\\n\", __func__);\n" - "> +=09=09return;\n" - "> +=09}\n" + "> +\tctx = rk3188_common_clk_init(np);\n" + "> +\tif (IS_ERR(ctx)) {\n" + "> +\t\tpr_err(\"%s: common clk init failed\\n\", __func__);\n" + "> +\t\treturn;\n" + "> +\t}\n" "\n" "I've dropped the pr_err + parentheses, as rk3188_common_clk_init\n" "will already output a suitable error.\n" "\n" "\n" "> +\n" - "> +=09rockchip_clk_register_plls(ctx, rk3066_pll_clks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3066_pll_clks),\n" - "> =09=09=09=09 RK3066_GRF_SOC_STATUS);\n" - "> -=09rockchip_clk_register_branches(rk3066a_clk_branches,\n" - "> +=09rockchip_clk_register_branches(ctx, rk3066a_clk_branches,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3066a_clk_branches));\n" - "> -=09rockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" - "> +=09rockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" - "> =09=09=09mux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" - "> =09=09=09&rk3066_cpuclk_data, rk3066_cpuclk_rates,\n" - "> =09=09=09ARRAY_SIZE(rk3066_cpuclk_rates));\n" - "> =09rockchip_clk_protect_critical(rk3188_critical_clocks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks));\n" - "> +=09rockchip_clk_of_add_provider(np, ctx);\n" + "> +\trockchip_clk_register_plls(ctx, rk3066_pll_clks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3066_pll_clks),\n" + "> \t\t\t\t RK3066_GRF_SOC_STATUS);\n" + "> -\trockchip_clk_register_branches(rk3066a_clk_branches,\n" + "> +\trockchip_clk_register_branches(ctx, rk3066a_clk_branches,\n" + "> \t\t\t\t ARRAY_SIZE(rk3066a_clk_branches));\n" + "> -\trockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" + "> +\trockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" + "> \t\t\tmux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" + "> \t\t\t&rk3066_cpuclk_data, rk3066_cpuclk_rates,\n" + "> \t\t\tARRAY_SIZE(rk3066_cpuclk_rates));\n" + "> \trockchip_clk_protect_critical(rk3188_critical_clocks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_critical_clocks));\n" + "> +\trockchip_clk_of_add_provider(np, ctx);\n" "> }\n" - "> CLK_OF_DECLARE(rk3066a_cru, \"rockchip,rk3066a-cru\", rk3066a_clk_init=\n" - ");\n" - ">=20\n" + "> CLK_OF_DECLARE(rk3066a_cru, \"rockchip,rk3066a-cru\", rk3066a_clk_init);\n" + "> \n" "> static void __init rk3188a_clk_init(struct device_node *np)\n" "> {\n" - "> +=09struct rockchip_clk_provider *ctx;\n" - "> =09struct clk *clk1, *clk2;\n" - "> =09unsigned long rate;\n" - "> =09int ret;\n" - ">=20\n" - "> -=09rk3188_common_clk_init(np);\n" - "> -=09rockchip_clk_register_plls(rk3188_pll_clks,\n" - "> +=09ctx =3D rk3188_common_clk_init(np);\n" - "> +=09if (IS_ERR(ctx)) {\n" - "> +=09=09pr_err(\"%s: common clk init failed\\n\", __func__);\n" - "> +=09=09return;\n" - "> +=09}\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" + "> \tstruct clk *clk1, *clk2;\n" + "> \tunsigned long rate;\n" + "> \tint ret;\n" + "> \n" + "> -\trk3188_common_clk_init(np);\n" + "> -\trockchip_clk_register_plls(rk3188_pll_clks,\n" + "> +\tctx = rk3188_common_clk_init(np);\n" + "> +\tif (IS_ERR(ctx)) {\n" + "> +\t\tpr_err(\"%s: common clk init failed\\n\", __func__);\n" + "> +\t\treturn;\n" + "> +\t}\n" "\n" "same as above\n" "\n" "\n" "> +\n" - "> +=09rockchip_clk_register_plls(ctx, rk3188_pll_clks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_pll_clks),\n" - "> =09=09=09=09 RK3188_GRF_SOC_STATUS);\n" - "> -=09rockchip_clk_register_branches(rk3188_clk_branches,\n" - "> +=09rockchip_clk_register_branches(ctx, rk3188_clk_branches,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_clk_branches));\n" - "> -=09rockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" - "> +=09rockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" - "> =09=09=09=09 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" - "> =09=09=09=09 &rk3188_cpuclk_data, rk3188_cpuclk_rates,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_cpuclk_rates));\n" - "> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device=\n" - "_node\n" + "> +\trockchip_clk_register_plls(ctx, rk3188_pll_clks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_pll_clks),\n" + "> \t\t\t\t RK3188_GRF_SOC_STATUS);\n" + "> -\trockchip_clk_register_branches(rk3188_clk_branches,\n" + "> +\trockchip_clk_register_branches(ctx, rk3188_clk_branches,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_clk_branches));\n" + "> -\trockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" + "> +\trockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" + "> \t\t\t\t mux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" + "> \t\t\t\t &rk3188_cpuclk_data, rk3188_cpuclk_rates,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_cpuclk_rates));\n" + "> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device_node\n" "> *np)\n" - ">=20\n" - "> =09rockchip_clk_protect_critical(rk3188_critical_clocks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks));\n" - "> +=09rockchip_clk_of_add_provider(np, ctx);\n" + "> \n" + "> \trockchip_clk_protect_critical(rk3188_critical_clocks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_critical_clocks));\n" + "> +\trockchip_clk_of_add_provider(np, ctx);\n" "> }\n" - "> CLK_OF_DECLARE(rk3188a_cru, \"rockchip,rk3188a-cru\", rk3188a_clk_init=\n" - ");\n" + "> CLK_OF_DECLARE(rk3188a_cru, \"rockchip,rk3188a-cru\", rk3188a_clk_init);\n" "\n" "[...]\n" "\n" @@ -189,7 +178,7 @@ "> @@ -312,66 +316,94 @@ static struct clk\n" "> *rockchip_clk_register_factor_branch(const char *name, return clk;\n" "> }\n" - ">=20\n" + "> \n" "> -static DEFINE_SPINLOCK(clk_lock);\n" "> -static struct clk **clk_table;\n" "> -static void __iomem *reg_base;\n" @@ -197,111 +186,102 @@ "> -static struct device_node *cru_node;\n" "> -static struct regmap *grf;\n" "> -\n" - "> -void __init rockchip_clk_init(struct device_node *np, void __iomem *=\n" - "base,\n" - "> -=09=09=09 unsigned long nr_clks)\n" - "> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device=\n" - "_node\n" + "> -void __init rockchip_clk_init(struct device_node *np, void __iomem *base,\n" + "> -\t\t\t unsigned long nr_clks)\n" + "> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device_node\n" "\n" "I've added a space between the asterisk and __init flag\n" "\n" "\n" - "> *np, +=09=09=09void __iomem *base, unsigned long nr_clks)\n" + "> *np, +\t\t\tvoid __iomem *base, unsigned long nr_clks)\n" "> {\n" - "> -=09reg_base =3D base;\n" - "> -=09cru_node =3D np;\n" - "> -=09grf =3D ERR_PTR(-EPROBE_DEFER);\n" - "> +=09struct rockchip_clk_provider *ctx;\n" - "> +=09struct clk **clk_table;\n" - "> +=09int i;\n" + "> -\treg_base = base;\n" + "> -\tcru_node = np;\n" + "> -\tgrf = ERR_PTR(-EPROBE_DEFER);\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" + "> +\tstruct clk **clk_table;\n" + "> +\tint i;\n" "> +\n" - "> +=09ctx =3D kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL)=\n" - ";\n" - "> +=09if (!ctx) {\n" - "> +=09=09pr_err(\"%s: Could not allocate clock provider context\\n\",\n" - "> +=09=09=09__func__);\n" - "> +=09=09return ERR_PTR(-ENOMEM);\n" - "> +=09}\n" - ">=20\n" - "> =09clk_table =3D kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);=\n" - "\n" - "> -=09if (!clk_table)\n" - "> -=09=09pr_err(\"%s: could not allocate clock lookup table\\n\", __func__=\n" - ");\n" - "> +=09if (!clk_table) {\n" - "> +=09=09pr_err(\"%s: Could not allocate clock lookup table\\n\",\n" - "> +=09=09=09__func__);\n" - "> +=09=09goto err_free;\n" - "> +=09}\n" + "> +\tctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);\n" + "> +\tif (!ctx) {\n" + "> +\t\tpr_err(\"%s: Could not allocate clock provider context\\n\",\n" + "> +\t\t\t__func__);\n" + "> +\t\treturn ERR_PTR(-ENOMEM);\n" + "> +\t}\n" + "> \n" + "> \tclk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);\n" + "> -\tif (!clk_table)\n" + "> -\t\tpr_err(\"%s: could not allocate clock lookup table\\n\", __func__);\n" + "> +\tif (!clk_table) {\n" + "> +\t\tpr_err(\"%s: Could not allocate clock lookup table\\n\",\n" + "> +\t\t\t__func__);\n" + "> +\t\tgoto err_free;\n" + "> +\t}\n" "> +\n" - "> +=09for (i =3D 0; i < nr_clks; ++i)\n" - "> +=09=09clk_table[i] =3D ERR_PTR(-ENOENT);\n" - ">=20\n" - "> -=09clk_data.clks =3D clk_table;\n" - "> -=09clk_data.clk_num =3D nr_clks;\n" - "> -=09of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n" - "> +=09ctx->reg_base =3D base;\n" - "> +=09ctx->clk_data.clks =3D clk_table;\n" - "> +=09ctx->clk_data.clk_num =3D nr_clks;\n" - "> +=09ctx->cru_node =3D np;\n" - "> +=09ctx->grf =3D ERR_PTR(-EPROBE_DEFER);\n" - "> +=09spin_lock_init(&ctx->lock);\n" + "> +\tfor (i = 0; i < nr_clks; ++i)\n" + "> +\t\tclk_table[i] = ERR_PTR(-ENOENT);\n" + "> \n" + "> -\tclk_data.clks = clk_table;\n" + "> -\tclk_data.clk_num = nr_clks;\n" + "> -\tof_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n" + "> +\tctx->reg_base = base;\n" + "> +\tctx->clk_data.clks = clk_table;\n" + "> +\tctx->clk_data.clk_num = nr_clks;\n" + "> +\tctx->cru_node = np;\n" + "> +\tctx->grf = ERR_PTR(-EPROBE_DEFER);\n" + "> +\tspin_lock_init(&ctx->lock);\n" "> +\n" - "> +=09return ctx;\n" + "> +\treturn ctx;\n" "> +\n" "> +err_free:\n" - "> +=09kfree(ctx);\n" - "> +=09return ERR_PTR(-ENOMEM);\n" + "> +\tkfree(ctx);\n" + "> +\treturn ERR_PTR(-ENOMEM);\n" "> +}\n" "> +\n" "> +void __init rockchip_clk_of_add_provider(struct device_node *np,\n" - "> +=09=09=09=09struct rockchip_clk_provider *ctx)\n" + "> +\t\t\t\tstruct rockchip_clk_provider *ctx)\n" "> +{\n" - "> +=09if (np) {\n" - "> +=09=09if (of_clk_add_provider(np, of_clk_src_onecell_get,\n" - "> +=09=09=09=09=09&ctx->clk_data))\n" - "> +=09=09=09panic(\"could not register clk provider\\n\");\n" + "> +\tif (np) {\n" + "> +\t\tif (of_clk_add_provider(np, of_clk_src_onecell_get,\n" + "> +\t\t\t\t\t&ctx->clk_data))\n" + "> +\t\t\tpanic(\"could not register clk provider\\n\");\n" "\n" - "I've changed that to a pr_err, again no need to panic on this, as letti=\n" - "ng\n" - "the kernel run may give the affected developer more hints what may be w=\n" - "rong.\n" + "I've changed that to a pr_err, again no need to panic on this, as letting\n" + "the kernel run may give the affected developer more hints what may be wrong.\n" "\n" "\n" - "> +=09}\n" + "> +\t}\n" "> }\n" - ">=20\n" + "> \n" "\n" "> diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h\n" "> index 7aafe18..b7affb6 100644\n" "> --- a/drivers/clk/rockchip/clk.h\n" "> +++ b/drivers/clk/rockchip/clk.h\n" "> @@ -127,6 +128,20 @@ enum rockchip_pll_type {\n" - "> =09.nb =3D _nb,=09=09=09=09=09=09\\\n" + "> \t.nb = _nb,\t\t\t\t\t\t\\\n" "> }\n" - ">=20\n" + "> \n" "> +/**\n" "> + * struct rockchip_clk_provider: information about clock provider\n" "> + * @reg_base: virtual address for the register base.\n" - "> + * @clk_data: holds clock related data like clk* and number of clock=\n" - "s.\n" - "> + * @lock: maintains exclusion between callbacks for a given clock-pr=\n" - "ovider.\n" + "> + * @clk_data: holds clock related data like clk* and number of clocks.\n" + "> + * @lock: maintains exclusion between callbacks for a given clock-provider.\n" "\n" "I've added the missing kerneldoc entries here\n" "\n" "\n" "> + */\n" "> +struct rockchip_clk_provider {\n" - "> +=09void __iomem *reg_base;\n" - "> +=09struct clk_onecell_data clk_data;\n" - "> +=09struct device_node *cru_node;\n" - "> +=09struct regmap *grf;\n" - "> +=09spinlock_t lock;\n" + "> +\tvoid __iomem *reg_base;\n" + "> +\tstruct clk_onecell_data clk_data;\n" + "> +\tstruct device_node *cru_node;\n" + "> +\tstruct regmap *grf;\n" + "> +\tspinlock_t lock;\n" "> +};\n" "> +\n" "> struct rockchip_pll_rate_table {\n" - "> =09unsigned long rate;\n" - > =09unsigned int nr; + "> \tunsigned long rate;\n" + "> \tunsigned int nr;" -cd95ff70f9686b9d2688dbd27d83f6d734f194e38e20fade16eeb68af63b0da3 +ef1f3a00557b599e8431daf4536e1ff77238111404b0c1f01a41f5cbf3b31d87
diff --git a/a/1.txt b/N2/1.txt index 948ea41..cb8ec5a 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,16 +1,15 @@ Hi Xing, -Am Mittwoch, 9. M=E4rz 2016, 10:37:04 schrieb Xing Zheng: +Am Mittwoch, 9. M?rz 2016, 10:37:04 schrieb Xing Zheng: > There are need to support Multi-CRUs probability in future, but > it is not supported on the current Rockchip Clock Framework. ->=20 +> > Therefore, this patch add support a provider as the parameter > handler when we call the clock register functions for per CRU. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> -I've applied that in a clk branch for 4.7 [0] with some changes detaile= -d +I've applied that in a clk branch for 4.7 [0] with some changes detailed below. If you can, please check that I didn't mess anything up :-) I've sucessfully booted that on both a rk3036 and rk3288 as well. @@ -18,16 +17,14 @@ I've sucessfully booted that on both a rk3036 and rk3288 as well. Heiko -[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g= -it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f= -864 +[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=d509ddf2e57c99ae760d1a289b85f1e0d729f864 > --- ->=20 +> > Changes in v3: None > Changes in v2: None ->=20 +> > drivers/clk/rockchip/clk-pll.c | 30 ++++---- > drivers/clk/rockchip/clk-rk3036.c | 17 +++-- > drivers/clk/rockchip/clk-rk3188.c | 48 ++++++++---- @@ -35,8 +32,7 @@ it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f= > drivers/clk/rockchip/clk-rk3288.c | 19 +++-- > drivers/clk/rockchip/clk-rk3368.c | 21 ++++-- > drivers/clk/rockchip/clk.c | 148 -> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h = - | =20 +> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h | > 49 ++++++++---- > 8 files changed, 231 insertions(+), 118 deletions(-) @@ -45,122 +41,115 @@ it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f= > diff --git a/drivers/clk/rockchip/clk-rk3188.c > b/drivers/clk/rockchip/clk-rk3188.c index e832403..7c73c51 100644 > --- a/drivers/clk/rockchip/clk-rk3188.c -> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks= -[] -> __initconst =3D { "hclk_cpubus" +> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks[] +> __initconst = { "hclk_cpubus" > }; ->=20 +> > -static void __init rk3188_common_clk_init(struct device_node *np) -> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(s= -truct +> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct > device_node *np) { -> +=09struct rockchip_clk_provider *ctx; -> =09void __iomem *reg_base; ->=20 -> =09reg_base =3D of_iomap(np, 0); -> =09if (!reg_base) { -> =09=09pr_err("%s: could not map cru region\n", __func__); -> -=09=09return; -> +=09=09return ERR_PTR(-ENOMEM); -> =09} ->=20 -> -=09rockchip_clk_init(np, reg_base, CLK_NR_CLKS); -> +=09ctx =3D rockchip_clk_init(np, reg_base, CLK_NR_CLKS); -> +=09if (IS_ERR(ctx)) { -> +=09=09pr_err("%s: rockchip clk init failed\n", __func__); -> +=09=09return ERR_PTR(-ENOMEM); -> +=09} ->=20 -> -=09rockchip_clk_register_branches(common_clk_branches, -> +=09rockchip_clk_register_branches(ctx, common_clk_branches, -> =09=09=09=09 ARRAY_SIZE(common_clk_branches)); ->=20 -> =09rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0)= -, -> =09=09=09=09 ROCKCHIP_SOFTRST_HIWORD_MASK); ->=20 -> -=09rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL); -> +=09rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL= -); +> + struct rockchip_clk_provider *ctx; +> void __iomem *reg_base; +> +> reg_base = of_iomap(np, 0); +> if (!reg_base) { +> pr_err("%s: could not map cru region\n", __func__); +> - return; +> + return ERR_PTR(-ENOMEM); +> } +> +> - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); +> + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); +> + if (IS_ERR(ctx)) { +> + pr_err("%s: rockchip clk init failed\n", __func__); +> + return ERR_PTR(-ENOMEM); +> + } +> +> - rockchip_clk_register_branches(common_clk_branches, +> + rockchip_clk_register_branches(ctx, common_clk_branches, +> ARRAY_SIZE(common_clk_branches)); +> +> rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), +> ROCKCHIP_SOFTRST_HIWORD_MASK); +> +> - rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL); +> + rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); > + -> +=09return ctx; +> + return ctx; > } ->=20 +> > static void __init rk3066a_clk_init(struct device_node *np) > { -> -=09rk3188_common_clk_init(np); -> -=09rockchip_clk_register_plls(rk3066_pll_clks, -> +=09struct rockchip_clk_provider *ctx; +> - rk3188_common_clk_init(np); +> - rockchip_clk_register_plls(rk3066_pll_clks, +> + struct rockchip_clk_provider *ctx; > + -> +=09ctx =3D rk3188_common_clk_init(np); -> +=09if (IS_ERR(ctx)) { -> +=09=09pr_err("%s: common clk init failed\n", __func__); -> +=09=09return; -> +=09} +> + ctx = rk3188_common_clk_init(np); +> + if (IS_ERR(ctx)) { +> + pr_err("%s: common clk init failed\n", __func__); +> + return; +> + } I've dropped the pr_err + parentheses, as rk3188_common_clk_init will already output a suitable error. > + -> +=09rockchip_clk_register_plls(ctx, rk3066_pll_clks, -> =09=09=09=09 ARRAY_SIZE(rk3066_pll_clks), -> =09=09=09=09 RK3066_GRF_SOC_STATUS); -> -=09rockchip_clk_register_branches(rk3066a_clk_branches, -> +=09rockchip_clk_register_branches(ctx, rk3066a_clk_branches, -> =09=09=09=09 ARRAY_SIZE(rk3066a_clk_branches)); -> -=09rockchip_clk_register_armclk(ARMCLK, "armclk", -> +=09rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", -> =09=09=09mux_armclk_p, ARRAY_SIZE(mux_armclk_p), -> =09=09=09&rk3066_cpuclk_data, rk3066_cpuclk_rates, -> =09=09=09ARRAY_SIZE(rk3066_cpuclk_rates)); -> =09rockchip_clk_protect_critical(rk3188_critical_clocks, -> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks)); -> +=09rockchip_clk_of_add_provider(np, ctx); +> + rockchip_clk_register_plls(ctx, rk3066_pll_clks, +> ARRAY_SIZE(rk3066_pll_clks), +> RK3066_GRF_SOC_STATUS); +> - rockchip_clk_register_branches(rk3066a_clk_branches, +> + rockchip_clk_register_branches(ctx, rk3066a_clk_branches, +> ARRAY_SIZE(rk3066a_clk_branches)); +> - rockchip_clk_register_armclk(ARMCLK, "armclk", +> + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", +> mux_armclk_p, ARRAY_SIZE(mux_armclk_p), +> &rk3066_cpuclk_data, rk3066_cpuclk_rates, +> ARRAY_SIZE(rk3066_cpuclk_rates)); +> rockchip_clk_protect_critical(rk3188_critical_clocks, +> ARRAY_SIZE(rk3188_critical_clocks)); +> + rockchip_clk_of_add_provider(np, ctx); > } -> CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init= -); ->=20 +> CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); +> > static void __init rk3188a_clk_init(struct device_node *np) > { -> +=09struct rockchip_clk_provider *ctx; -> =09struct clk *clk1, *clk2; -> =09unsigned long rate; -> =09int ret; ->=20 -> -=09rk3188_common_clk_init(np); -> -=09rockchip_clk_register_plls(rk3188_pll_clks, -> +=09ctx =3D rk3188_common_clk_init(np); -> +=09if (IS_ERR(ctx)) { -> +=09=09pr_err("%s: common clk init failed\n", __func__); -> +=09=09return; -> +=09} +> + struct rockchip_clk_provider *ctx; +> struct clk *clk1, *clk2; +> unsigned long rate; +> int ret; +> +> - rk3188_common_clk_init(np); +> - rockchip_clk_register_plls(rk3188_pll_clks, +> + ctx = rk3188_common_clk_init(np); +> + if (IS_ERR(ctx)) { +> + pr_err("%s: common clk init failed\n", __func__); +> + return; +> + } same as above > + -> +=09rockchip_clk_register_plls(ctx, rk3188_pll_clks, -> =09=09=09=09 ARRAY_SIZE(rk3188_pll_clks), -> =09=09=09=09 RK3188_GRF_SOC_STATUS); -> -=09rockchip_clk_register_branches(rk3188_clk_branches, -> +=09rockchip_clk_register_branches(ctx, rk3188_clk_branches, -> =09=09=09=09 ARRAY_SIZE(rk3188_clk_branches)); -> -=09rockchip_clk_register_armclk(ARMCLK, "armclk", -> +=09rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", -> =09=09=09=09 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), -> =09=09=09=09 &rk3188_cpuclk_data, rk3188_cpuclk_rates, -> =09=09=09=09 ARRAY_SIZE(rk3188_cpuclk_rates)); -> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device= -_node +> + rockchip_clk_register_plls(ctx, rk3188_pll_clks, +> ARRAY_SIZE(rk3188_pll_clks), +> RK3188_GRF_SOC_STATUS); +> - rockchip_clk_register_branches(rk3188_clk_branches, +> + rockchip_clk_register_branches(ctx, rk3188_clk_branches, +> ARRAY_SIZE(rk3188_clk_branches)); +> - rockchip_clk_register_armclk(ARMCLK, "armclk", +> + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", +> mux_armclk_p, ARRAY_SIZE(mux_armclk_p), +> &rk3188_cpuclk_data, rk3188_cpuclk_rates, +> ARRAY_SIZE(rk3188_cpuclk_rates)); +> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device_node > *np) ->=20 -> =09rockchip_clk_protect_critical(rk3188_critical_clocks, -> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks)); -> +=09rockchip_clk_of_add_provider(np, ctx); +> +> rockchip_clk_protect_critical(rk3188_critical_clocks, +> ARRAY_SIZE(rk3188_critical_clocks)); +> + rockchip_clk_of_add_provider(np, ctx); > } -> CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init= -); +> CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); [...] @@ -171,7 +160,7 @@ _node > @@ -312,66 +316,94 @@ static struct clk > *rockchip_clk_register_factor_branch(const char *name, return clk; > } ->=20 +> > -static DEFINE_SPINLOCK(clk_lock); > -static struct clk **clk_table; > -static void __iomem *reg_base; @@ -179,109 +168,100 @@ _node > -static struct device_node *cru_node; > -static struct regmap *grf; > - -> -void __init rockchip_clk_init(struct device_node *np, void __iomem *= -base, -> -=09=09=09 unsigned long nr_clks) -> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device= -_node +> -void __init rockchip_clk_init(struct device_node *np, void __iomem *base, +> - unsigned long nr_clks) +> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device_node I've added a space between the asterisk and __init flag -> *np, +=09=09=09void __iomem *base, unsigned long nr_clks) +> *np, + void __iomem *base, unsigned long nr_clks) > { -> -=09reg_base =3D base; -> -=09cru_node =3D np; -> -=09grf =3D ERR_PTR(-EPROBE_DEFER); -> +=09struct rockchip_clk_provider *ctx; -> +=09struct clk **clk_table; -> +=09int i; +> - reg_base = base; +> - cru_node = np; +> - grf = ERR_PTR(-EPROBE_DEFER); +> + struct rockchip_clk_provider *ctx; +> + struct clk **clk_table; +> + int i; > + -> +=09ctx =3D kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL)= -; -> +=09if (!ctx) { -> +=09=09pr_err("%s: Could not allocate clock provider context\n", -> +=09=09=09__func__); -> +=09=09return ERR_PTR(-ENOMEM); -> +=09} ->=20 -> =09clk_table =3D kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);= - -> -=09if (!clk_table) -> -=09=09pr_err("%s: could not allocate clock lookup table\n", __func__= -); -> +=09if (!clk_table) { -> +=09=09pr_err("%s: Could not allocate clock lookup table\n", -> +=09=09=09__func__); -> +=09=09goto err_free; -> +=09} +> + ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); +> + if (!ctx) { +> + pr_err("%s: Could not allocate clock provider context\n", +> + __func__); +> + return ERR_PTR(-ENOMEM); +> + } +> +> clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); +> - if (!clk_table) +> - pr_err("%s: could not allocate clock lookup table\n", __func__); +> + if (!clk_table) { +> + pr_err("%s: Could not allocate clock lookup table\n", +> + __func__); +> + goto err_free; +> + } > + -> +=09for (i =3D 0; i < nr_clks; ++i) -> +=09=09clk_table[i] =3D ERR_PTR(-ENOENT); ->=20 -> -=09clk_data.clks =3D clk_table; -> -=09clk_data.clk_num =3D nr_clks; -> -=09of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -> +=09ctx->reg_base =3D base; -> +=09ctx->clk_data.clks =3D clk_table; -> +=09ctx->clk_data.clk_num =3D nr_clks; -> +=09ctx->cru_node =3D np; -> +=09ctx->grf =3D ERR_PTR(-EPROBE_DEFER); -> +=09spin_lock_init(&ctx->lock); +> + for (i = 0; i < nr_clks; ++i) +> + clk_table[i] = ERR_PTR(-ENOENT); +> +> - clk_data.clks = clk_table; +> - clk_data.clk_num = nr_clks; +> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +> + ctx->reg_base = base; +> + ctx->clk_data.clks = clk_table; +> + ctx->clk_data.clk_num = nr_clks; +> + ctx->cru_node = np; +> + ctx->grf = ERR_PTR(-EPROBE_DEFER); +> + spin_lock_init(&ctx->lock); > + -> +=09return ctx; +> + return ctx; > + > +err_free: -> +=09kfree(ctx); -> +=09return ERR_PTR(-ENOMEM); +> + kfree(ctx); +> + return ERR_PTR(-ENOMEM); > +} > + > +void __init rockchip_clk_of_add_provider(struct device_node *np, -> +=09=09=09=09struct rockchip_clk_provider *ctx) +> + struct rockchip_clk_provider *ctx) > +{ -> +=09if (np) { -> +=09=09if (of_clk_add_provider(np, of_clk_src_onecell_get, -> +=09=09=09=09=09&ctx->clk_data)) -> +=09=09=09panic("could not register clk provider\n"); +> + if (np) { +> + if (of_clk_add_provider(np, of_clk_src_onecell_get, +> + &ctx->clk_data)) +> + panic("could not register clk provider\n"); -I've changed that to a pr_err, again no need to panic on this, as letti= -ng -the kernel run may give the affected developer more hints what may be w= -rong. +I've changed that to a pr_err, again no need to panic on this, as letting +the kernel run may give the affected developer more hints what may be wrong. -> +=09} +> + } > } ->=20 +> > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index 7aafe18..b7affb6 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -127,6 +128,20 @@ enum rockchip_pll_type { -> =09.nb =3D _nb,=09=09=09=09=09=09\ +> .nb = _nb, \ > } ->=20 +> > +/** > + * struct rockchip_clk_provider: information about clock provider > + * @reg_base: virtual address for the register base. -> + * @clk_data: holds clock related data like clk* and number of clock= -s. -> + * @lock: maintains exclusion between callbacks for a given clock-pr= -ovider. +> + * @clk_data: holds clock related data like clk* and number of clocks. +> + * @lock: maintains exclusion between callbacks for a given clock-provider. I've added the missing kerneldoc entries here > + */ > +struct rockchip_clk_provider { -> +=09void __iomem *reg_base; -> +=09struct clk_onecell_data clk_data; -> +=09struct device_node *cru_node; -> +=09struct regmap *grf; -> +=09spinlock_t lock; +> + void __iomem *reg_base; +> + struct clk_onecell_data clk_data; +> + struct device_node *cru_node; +> + struct regmap *grf; +> + spinlock_t lock; > +}; > + > struct rockchip_pll_rate_table { -> =09unsigned long rate; -> =09unsigned int nr; +> unsigned long rate; +> unsigned int nr; diff --git a/a/content_digest b/N2/content_digest index 35e221b..8aa8801 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,34 +1,23 @@ "ref\01457491027-30936-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01457491027-30936-5-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v3 4/7] clk: rockchip: Add support for multiple clock providers\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "Subject\0[PATCH v3 4/7] clk: rockchip: Add support for multiple clock providers\0" "Date\0Wed, 09 Mar 2016 23:25:42 +0100\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - huangtao@rock-chips.com - jay.xu@rock-chips.com - elaine.zhang@rock-chips.com - dianders@chromium.org - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Xing,\n" "\n" - "Am Mittwoch, 9. M=E4rz 2016, 10:37:04 schrieb Xing Zheng:\n" + "Am Mittwoch, 9. M?rz 2016, 10:37:04 schrieb Xing Zheng:\n" "> There are need to support Multi-CRUs probability in future, but\n" "> it is not supported on the current Rockchip Clock Framework.\n" - ">=20\n" + "> \n" "> Therefore, this patch add support a provider as the parameter\n" "> handler when we call the clock register functions for per CRU.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" - "I've applied that in a clk branch for 4.7 [0] with some changes detaile=\n" - "d\n" + "I've applied that in a clk branch for 4.7 [0] with some changes detailed\n" "below. If you can, please check that I didn't mess anything up :-)\n" "\n" "I've sucessfully booted that on both a rk3036 and rk3288 as well.\n" @@ -36,16 +25,14 @@ "\n" "Heiko\n" "\n" - "[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g=\n" - "it/commit/?h=3Dv4.7-clk/next&id=3Dd509ddf2e57c99ae760d1a289b85f1e0d729f=\n" - "864\n" + "[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=d509ddf2e57c99ae760d1a289b85f1e0d729f864\n" "\n" "\n" "> ---\n" - ">=20\n" + "> \n" "> Changes in v3: None\n" "> Changes in v2: None\n" - ">=20\n" + "> \n" "> drivers/clk/rockchip/clk-pll.c | 30 ++++----\n" "> drivers/clk/rockchip/clk-rk3036.c | 17 +++--\n" "> drivers/clk/rockchip/clk-rk3188.c | 48 ++++++++----\n" @@ -53,8 +40,7 @@ "> drivers/clk/rockchip/clk-rk3288.c | 19 +++--\n" "> drivers/clk/rockchip/clk-rk3368.c | 21 ++++--\n" "> drivers/clk/rockchip/clk.c | 148\n" - "> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h =\n" - " | =20\n" + "> +++++++++++++++++++++++-------------- drivers/clk/rockchip/clk.h | \n" "> 49 ++++++++----\n" "> 8 files changed, 231 insertions(+), 118 deletions(-)\n" "\n" @@ -63,122 +49,115 @@ "> diff --git a/drivers/clk/rockchip/clk-rk3188.c\n" "> b/drivers/clk/rockchip/clk-rk3188.c index e832403..7c73c51 100644\n" "> --- a/drivers/clk/rockchip/clk-rk3188.c\n" - "> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks=\n" - "[]\n" - "> __initconst =3D { \"hclk_cpubus\"\n" + "> @@ -759,57 +759,78 @@ static const char *const rk3188_critical_clocks[]\n" + "> __initconst = { \"hclk_cpubus\"\n" "> };\n" - ">=20\n" + "> \n" "> -static void __init rk3188_common_clk_init(struct device_node *np)\n" - "> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(s=\n" - "truct\n" + "> +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct\n" "> device_node *np) {\n" - "> +=09struct rockchip_clk_provider *ctx;\n" - "> =09void __iomem *reg_base;\n" - ">=20\n" - "> =09reg_base =3D of_iomap(np, 0);\n" - "> =09if (!reg_base) {\n" - "> =09=09pr_err(\"%s: could not map cru region\\n\", __func__);\n" - "> -=09=09return;\n" - "> +=09=09return ERR_PTR(-ENOMEM);\n" - "> =09}\n" - ">=20\n" - "> -=09rockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" - "> +=09ctx =3D rockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" - "> +=09if (IS_ERR(ctx)) {\n" - "> +=09=09pr_err(\"%s: rockchip clk init failed\\n\", __func__);\n" - "> +=09=09return ERR_PTR(-ENOMEM);\n" - "> +=09}\n" - ">=20\n" - "> -=09rockchip_clk_register_branches(common_clk_branches,\n" - "> +=09rockchip_clk_register_branches(ctx, common_clk_branches,\n" - "> =09=09=09=09 ARRAY_SIZE(common_clk_branches));\n" - ">=20\n" - "> =09rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0)=\n" - ",\n" - "> =09=09=09=09 ROCKCHIP_SOFTRST_HIWORD_MASK);\n" - ">=20\n" - "> -=09rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);\n" - "> +=09rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL=\n" - ");\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" + "> \tvoid __iomem *reg_base;\n" + "> \n" + "> \treg_base = of_iomap(np, 0);\n" + "> \tif (!reg_base) {\n" + "> \t\tpr_err(\"%s: could not map cru region\\n\", __func__);\n" + "> -\t\treturn;\n" + "> +\t\treturn ERR_PTR(-ENOMEM);\n" + "> \t}\n" + "> \n" + "> -\trockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" + "> +\tctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);\n" + "> +\tif (IS_ERR(ctx)) {\n" + "> +\t\tpr_err(\"%s: rockchip clk init failed\\n\", __func__);\n" + "> +\t\treturn ERR_PTR(-ENOMEM);\n" + "> +\t}\n" + "> \n" + "> -\trockchip_clk_register_branches(common_clk_branches,\n" + "> +\trockchip_clk_register_branches(ctx, common_clk_branches,\n" + "> \t\t\t\t ARRAY_SIZE(common_clk_branches));\n" + "> \n" + "> \trockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),\n" + "> \t\t\t\t ROCKCHIP_SOFTRST_HIWORD_MASK);\n" + "> \n" + "> -\trockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);\n" + "> +\trockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);\n" "> +\n" - "> +=09return ctx;\n" + "> +\treturn ctx;\n" "> }\n" - ">=20\n" + "> \n" "> static void __init rk3066a_clk_init(struct device_node *np)\n" "> {\n" - "> -=09rk3188_common_clk_init(np);\n" - "> -=09rockchip_clk_register_plls(rk3066_pll_clks,\n" - "> +=09struct rockchip_clk_provider *ctx;\n" + "> -\trk3188_common_clk_init(np);\n" + "> -\trockchip_clk_register_plls(rk3066_pll_clks,\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" "> +\n" - "> +=09ctx =3D rk3188_common_clk_init(np);\n" - "> +=09if (IS_ERR(ctx)) {\n" - "> +=09=09pr_err(\"%s: common clk init failed\\n\", __func__);\n" - "> +=09=09return;\n" - "> +=09}\n" + "> +\tctx = rk3188_common_clk_init(np);\n" + "> +\tif (IS_ERR(ctx)) {\n" + "> +\t\tpr_err(\"%s: common clk init failed\\n\", __func__);\n" + "> +\t\treturn;\n" + "> +\t}\n" "\n" "I've dropped the pr_err + parentheses, as rk3188_common_clk_init\n" "will already output a suitable error.\n" "\n" "\n" "> +\n" - "> +=09rockchip_clk_register_plls(ctx, rk3066_pll_clks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3066_pll_clks),\n" - "> =09=09=09=09 RK3066_GRF_SOC_STATUS);\n" - "> -=09rockchip_clk_register_branches(rk3066a_clk_branches,\n" - "> +=09rockchip_clk_register_branches(ctx, rk3066a_clk_branches,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3066a_clk_branches));\n" - "> -=09rockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" - "> +=09rockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" - "> =09=09=09mux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" - "> =09=09=09&rk3066_cpuclk_data, rk3066_cpuclk_rates,\n" - "> =09=09=09ARRAY_SIZE(rk3066_cpuclk_rates));\n" - "> =09rockchip_clk_protect_critical(rk3188_critical_clocks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks));\n" - "> +=09rockchip_clk_of_add_provider(np, ctx);\n" + "> +\trockchip_clk_register_plls(ctx, rk3066_pll_clks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3066_pll_clks),\n" + "> \t\t\t\t RK3066_GRF_SOC_STATUS);\n" + "> -\trockchip_clk_register_branches(rk3066a_clk_branches,\n" + "> +\trockchip_clk_register_branches(ctx, rk3066a_clk_branches,\n" + "> \t\t\t\t ARRAY_SIZE(rk3066a_clk_branches));\n" + "> -\trockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" + "> +\trockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" + "> \t\t\tmux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" + "> \t\t\t&rk3066_cpuclk_data, rk3066_cpuclk_rates,\n" + "> \t\t\tARRAY_SIZE(rk3066_cpuclk_rates));\n" + "> \trockchip_clk_protect_critical(rk3188_critical_clocks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_critical_clocks));\n" + "> +\trockchip_clk_of_add_provider(np, ctx);\n" "> }\n" - "> CLK_OF_DECLARE(rk3066a_cru, \"rockchip,rk3066a-cru\", rk3066a_clk_init=\n" - ");\n" - ">=20\n" + "> CLK_OF_DECLARE(rk3066a_cru, \"rockchip,rk3066a-cru\", rk3066a_clk_init);\n" + "> \n" "> static void __init rk3188a_clk_init(struct device_node *np)\n" "> {\n" - "> +=09struct rockchip_clk_provider *ctx;\n" - "> =09struct clk *clk1, *clk2;\n" - "> =09unsigned long rate;\n" - "> =09int ret;\n" - ">=20\n" - "> -=09rk3188_common_clk_init(np);\n" - "> -=09rockchip_clk_register_plls(rk3188_pll_clks,\n" - "> +=09ctx =3D rk3188_common_clk_init(np);\n" - "> +=09if (IS_ERR(ctx)) {\n" - "> +=09=09pr_err(\"%s: common clk init failed\\n\", __func__);\n" - "> +=09=09return;\n" - "> +=09}\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" + "> \tstruct clk *clk1, *clk2;\n" + "> \tunsigned long rate;\n" + "> \tint ret;\n" + "> \n" + "> -\trk3188_common_clk_init(np);\n" + "> -\trockchip_clk_register_plls(rk3188_pll_clks,\n" + "> +\tctx = rk3188_common_clk_init(np);\n" + "> +\tif (IS_ERR(ctx)) {\n" + "> +\t\tpr_err(\"%s: common clk init failed\\n\", __func__);\n" + "> +\t\treturn;\n" + "> +\t}\n" "\n" "same as above\n" "\n" "\n" "> +\n" - "> +=09rockchip_clk_register_plls(ctx, rk3188_pll_clks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_pll_clks),\n" - "> =09=09=09=09 RK3188_GRF_SOC_STATUS);\n" - "> -=09rockchip_clk_register_branches(rk3188_clk_branches,\n" - "> +=09rockchip_clk_register_branches(ctx, rk3188_clk_branches,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_clk_branches));\n" - "> -=09rockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" - "> +=09rockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" - "> =09=09=09=09 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" - "> =09=09=09=09 &rk3188_cpuclk_data, rk3188_cpuclk_rates,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_cpuclk_rates));\n" - "> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device=\n" - "_node\n" + "> +\trockchip_clk_register_plls(ctx, rk3188_pll_clks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_pll_clks),\n" + "> \t\t\t\t RK3188_GRF_SOC_STATUS);\n" + "> -\trockchip_clk_register_branches(rk3188_clk_branches,\n" + "> +\trockchip_clk_register_branches(ctx, rk3188_clk_branches,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_clk_branches));\n" + "> -\trockchip_clk_register_armclk(ARMCLK, \"armclk\",\n" + "> +\trockchip_clk_register_armclk(ctx, ARMCLK, \"armclk\",\n" + "> \t\t\t\t mux_armclk_p, ARRAY_SIZE(mux_armclk_p),\n" + "> \t\t\t\t &rk3188_cpuclk_data, rk3188_cpuclk_rates,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_cpuclk_rates));\n" + "> @@ -833,6 +854,7 @@ static void __init rk3188a_clk_init(struct device_node\n" "> *np)\n" - ">=20\n" - "> =09rockchip_clk_protect_critical(rk3188_critical_clocks,\n" - "> =09=09=09=09 ARRAY_SIZE(rk3188_critical_clocks));\n" - "> +=09rockchip_clk_of_add_provider(np, ctx);\n" + "> \n" + "> \trockchip_clk_protect_critical(rk3188_critical_clocks,\n" + "> \t\t\t\t ARRAY_SIZE(rk3188_critical_clocks));\n" + "> +\trockchip_clk_of_add_provider(np, ctx);\n" "> }\n" - "> CLK_OF_DECLARE(rk3188a_cru, \"rockchip,rk3188a-cru\", rk3188a_clk_init=\n" - ");\n" + "> CLK_OF_DECLARE(rk3188a_cru, \"rockchip,rk3188a-cru\", rk3188a_clk_init);\n" "\n" "[...]\n" "\n" @@ -189,7 +168,7 @@ "> @@ -312,66 +316,94 @@ static struct clk\n" "> *rockchip_clk_register_factor_branch(const char *name, return clk;\n" "> }\n" - ">=20\n" + "> \n" "> -static DEFINE_SPINLOCK(clk_lock);\n" "> -static struct clk **clk_table;\n" "> -static void __iomem *reg_base;\n" @@ -197,111 +176,102 @@ "> -static struct device_node *cru_node;\n" "> -static struct regmap *grf;\n" "> -\n" - "> -void __init rockchip_clk_init(struct device_node *np, void __iomem *=\n" - "base,\n" - "> -=09=09=09 unsigned long nr_clks)\n" - "> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device=\n" - "_node\n" + "> -void __init rockchip_clk_init(struct device_node *np, void __iomem *base,\n" + "> -\t\t\t unsigned long nr_clks)\n" + "> +struct rockchip_clk_provider *__init rockchip_clk_init(struct device_node\n" "\n" "I've added a space between the asterisk and __init flag\n" "\n" "\n" - "> *np, +=09=09=09void __iomem *base, unsigned long nr_clks)\n" + "> *np, +\t\t\tvoid __iomem *base, unsigned long nr_clks)\n" "> {\n" - "> -=09reg_base =3D base;\n" - "> -=09cru_node =3D np;\n" - "> -=09grf =3D ERR_PTR(-EPROBE_DEFER);\n" - "> +=09struct rockchip_clk_provider *ctx;\n" - "> +=09struct clk **clk_table;\n" - "> +=09int i;\n" + "> -\treg_base = base;\n" + "> -\tcru_node = np;\n" + "> -\tgrf = ERR_PTR(-EPROBE_DEFER);\n" + "> +\tstruct rockchip_clk_provider *ctx;\n" + "> +\tstruct clk **clk_table;\n" + "> +\tint i;\n" "> +\n" - "> +=09ctx =3D kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL)=\n" - ";\n" - "> +=09if (!ctx) {\n" - "> +=09=09pr_err(\"%s: Could not allocate clock provider context\\n\",\n" - "> +=09=09=09__func__);\n" - "> +=09=09return ERR_PTR(-ENOMEM);\n" - "> +=09}\n" - ">=20\n" - "> =09clk_table =3D kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);=\n" - "\n" - "> -=09if (!clk_table)\n" - "> -=09=09pr_err(\"%s: could not allocate clock lookup table\\n\", __func__=\n" - ");\n" - "> +=09if (!clk_table) {\n" - "> +=09=09pr_err(\"%s: Could not allocate clock lookup table\\n\",\n" - "> +=09=09=09__func__);\n" - "> +=09=09goto err_free;\n" - "> +=09}\n" + "> +\tctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);\n" + "> +\tif (!ctx) {\n" + "> +\t\tpr_err(\"%s: Could not allocate clock provider context\\n\",\n" + "> +\t\t\t__func__);\n" + "> +\t\treturn ERR_PTR(-ENOMEM);\n" + "> +\t}\n" + "> \n" + "> \tclk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);\n" + "> -\tif (!clk_table)\n" + "> -\t\tpr_err(\"%s: could not allocate clock lookup table\\n\", __func__);\n" + "> +\tif (!clk_table) {\n" + "> +\t\tpr_err(\"%s: Could not allocate clock lookup table\\n\",\n" + "> +\t\t\t__func__);\n" + "> +\t\tgoto err_free;\n" + "> +\t}\n" "> +\n" - "> +=09for (i =3D 0; i < nr_clks; ++i)\n" - "> +=09=09clk_table[i] =3D ERR_PTR(-ENOENT);\n" - ">=20\n" - "> -=09clk_data.clks =3D clk_table;\n" - "> -=09clk_data.clk_num =3D nr_clks;\n" - "> -=09of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n" - "> +=09ctx->reg_base =3D base;\n" - "> +=09ctx->clk_data.clks =3D clk_table;\n" - "> +=09ctx->clk_data.clk_num =3D nr_clks;\n" - "> +=09ctx->cru_node =3D np;\n" - "> +=09ctx->grf =3D ERR_PTR(-EPROBE_DEFER);\n" - "> +=09spin_lock_init(&ctx->lock);\n" + "> +\tfor (i = 0; i < nr_clks; ++i)\n" + "> +\t\tclk_table[i] = ERR_PTR(-ENOENT);\n" + "> \n" + "> -\tclk_data.clks = clk_table;\n" + "> -\tclk_data.clk_num = nr_clks;\n" + "> -\tof_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n" + "> +\tctx->reg_base = base;\n" + "> +\tctx->clk_data.clks = clk_table;\n" + "> +\tctx->clk_data.clk_num = nr_clks;\n" + "> +\tctx->cru_node = np;\n" + "> +\tctx->grf = ERR_PTR(-EPROBE_DEFER);\n" + "> +\tspin_lock_init(&ctx->lock);\n" "> +\n" - "> +=09return ctx;\n" + "> +\treturn ctx;\n" "> +\n" "> +err_free:\n" - "> +=09kfree(ctx);\n" - "> +=09return ERR_PTR(-ENOMEM);\n" + "> +\tkfree(ctx);\n" + "> +\treturn ERR_PTR(-ENOMEM);\n" "> +}\n" "> +\n" "> +void __init rockchip_clk_of_add_provider(struct device_node *np,\n" - "> +=09=09=09=09struct rockchip_clk_provider *ctx)\n" + "> +\t\t\t\tstruct rockchip_clk_provider *ctx)\n" "> +{\n" - "> +=09if (np) {\n" - "> +=09=09if (of_clk_add_provider(np, of_clk_src_onecell_get,\n" - "> +=09=09=09=09=09&ctx->clk_data))\n" - "> +=09=09=09panic(\"could not register clk provider\\n\");\n" + "> +\tif (np) {\n" + "> +\t\tif (of_clk_add_provider(np, of_clk_src_onecell_get,\n" + "> +\t\t\t\t\t&ctx->clk_data))\n" + "> +\t\t\tpanic(\"could not register clk provider\\n\");\n" "\n" - "I've changed that to a pr_err, again no need to panic on this, as letti=\n" - "ng\n" - "the kernel run may give the affected developer more hints what may be w=\n" - "rong.\n" + "I've changed that to a pr_err, again no need to panic on this, as letting\n" + "the kernel run may give the affected developer more hints what may be wrong.\n" "\n" "\n" - "> +=09}\n" + "> +\t}\n" "> }\n" - ">=20\n" + "> \n" "\n" "> diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h\n" "> index 7aafe18..b7affb6 100644\n" "> --- a/drivers/clk/rockchip/clk.h\n" "> +++ b/drivers/clk/rockchip/clk.h\n" "> @@ -127,6 +128,20 @@ enum rockchip_pll_type {\n" - "> =09.nb =3D _nb,=09=09=09=09=09=09\\\n" + "> \t.nb = _nb,\t\t\t\t\t\t\\\n" "> }\n" - ">=20\n" + "> \n" "> +/**\n" "> + * struct rockchip_clk_provider: information about clock provider\n" "> + * @reg_base: virtual address for the register base.\n" - "> + * @clk_data: holds clock related data like clk* and number of clock=\n" - "s.\n" - "> + * @lock: maintains exclusion between callbacks for a given clock-pr=\n" - "ovider.\n" + "> + * @clk_data: holds clock related data like clk* and number of clocks.\n" + "> + * @lock: maintains exclusion between callbacks for a given clock-provider.\n" "\n" "I've added the missing kerneldoc entries here\n" "\n" "\n" "> + */\n" "> +struct rockchip_clk_provider {\n" - "> +=09void __iomem *reg_base;\n" - "> +=09struct clk_onecell_data clk_data;\n" - "> +=09struct device_node *cru_node;\n" - "> +=09struct regmap *grf;\n" - "> +=09spinlock_t lock;\n" + "> +\tvoid __iomem *reg_base;\n" + "> +\tstruct clk_onecell_data clk_data;\n" + "> +\tstruct device_node *cru_node;\n" + "> +\tstruct regmap *grf;\n" + "> +\tspinlock_t lock;\n" "> +};\n" "> +\n" "> struct rockchip_pll_rate_table {\n" - "> =09unsigned long rate;\n" - > =09unsigned int nr; + "> \tunsigned long rate;\n" + "> \tunsigned int nr;" -cd95ff70f9686b9d2688dbd27d83f6d734f194e38e20fade16eeb68af63b0da3 +9b6f043c0cf6cd05d29cb55264fda7ec1c5500d1d3df4cb926d687800bf8d55b
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