From: Neeraj Kumar <s.neeraj@samsung.com>
To: Ira Weiny <ira.weiny@intel.com>
Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev,
linux-kernel@vger.kernel.org, gost.dev@samsung.com,
a.manzanares@samsung.com, vishak.g@samsung.com,
neeraj.kernel@gmail.com, cpgs@samsung.com
Subject: Re: [PATCH V2 03/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1
Date: Thu, 4 Sep 2025 19:21:13 +0530 [thread overview]
Message-ID: <1983025922.01757055782611.JavaMail.epsvc@epcpadp2new> (raw)
In-Reply-To: <68a49f05796ef_27db95294cf@iweiny-mobl.notmuch>
[-- Attachment #1: Type: text/plain, Size: 5221 bytes --]
On 19/08/25 10:57AM, Ira Weiny wrote:
>Neeraj Kumar wrote:
>> CXL 3.2 Spec mentions CXL LSA 2.1 Namespace Labels at section 9.13.2.5
>> Modified __pmem_label_update function using setter functions to update
>> namespace label as per CXL LSA 2.1
>
>But why? And didn't we just remove nd_namespace_label in patch 2?
>
>Why are we now defining accessor functions for it?
>
Hi Ira,
No we haven't removed nd_namespace_label in patch 2. In patch 2, we have
introduced
lsa_label which contains nd_namespace_label as well as cxl_region_label
under union.
Actually, LSA 2.1 spec introduced new region label along with existing
(v1.1 & v1.2) namespace label
But in v2.1 namespace label members are also modified compared to v1.1 &
v1.2.
New members introduced in namespace label are following
struct nvdimm_cxl_label {
u8 type[NSLABEL_UUID_LEN]; --> Filling it with nsl_set_type()
u8 uuid[NSLABEL_UUID_LEN];
u8 name[NSLABEL_NAME_LEN];
__le32 flags;
__le16 nrange;
__le16 position;
__le64 dpa;
__le64 rawsize;
__le32 slot;
__le32 align; --> Filling it with
nsl_set_alignment()
u8 region_uuid[16]; --> Filling it with
nsl_set_region_uuid()
u8 abstraction_uuid[16];
__le16 lbasize;
u8 reserved[0x56];
__le64 checksum;
};
Therefore this patch-set address this modification in namespace label as per v2.1
>>
>> Signed-off-by: Neeraj Kumar <s.neeraj@samsung.com>
>> ---
>> drivers/nvdimm/label.c | 3 +++
>> drivers/nvdimm/nd.h | 27 +++++++++++++++++++++++++++
>> 2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/nvdimm/label.c b/drivers/nvdimm/label.c
>> index 75bc11da4c11..3f8a6bdb77c7 100644
>> --- a/drivers/nvdimm/label.c
>> +++ b/drivers/nvdimm/label.c
>> @@ -933,6 +933,7 @@ static int __pmem_label_update(struct nd_region *nd_region,
>> memset(lsa_label, 0, sizeof_namespace_label(ndd));
>>
>> nd_label = &lsa_label->ns_label;
>> + nsl_set_type(ndd, nd_label);
>> nsl_set_uuid(ndd, nd_label, nspm->uuid);
>> nsl_set_name(ndd, nd_label, nspm->alt_name);
>> nsl_set_flags(ndd, nd_label, flags);
>> @@ -944,7 +945,9 @@ static int __pmem_label_update(struct nd_region *nd_region,
>> nsl_set_lbasize(ndd, nd_label, nspm->lbasize);
>> nsl_set_dpa(ndd, nd_label, res->start);
>> nsl_set_slot(ndd, nd_label, slot);
>> + nsl_set_alignment(ndd, nd_label, 0);
>> nsl_set_type_guid(ndd, nd_label, &nd_set->type_guid);
>> + nsl_set_region_uuid(ndd, nd_label, NULL);
>> nsl_set_claim_class(ndd, nd_label, ndns->claim_class);
>> nsl_calculate_checksum(ndd, nd_label);
>> nd_dbg_dpa(nd_region, ndd, res, "\n");
>> diff --git a/drivers/nvdimm/nd.h b/drivers/nvdimm/nd.h
>> index 61348dee687d..651847f1bbf9 100644
>> --- a/drivers/nvdimm/nd.h
>> +++ b/drivers/nvdimm/nd.h
>> @@ -295,6 +295,33 @@ static inline const u8 *nsl_uuid_raw(struct nvdimm_drvdata *ndd,
>> return nd_label->efi.uuid;
>> }
>>
>> +static inline void nsl_set_type(struct nvdimm_drvdata *ndd,
>> + struct nd_namespace_label *ns_label)
>
>Set type to what?
>
LSA 2.1 spec mentions seperate UUID for namespace label and region
label.
#define CXL_REGION_UUID "529d7c61-da07-47c4-a93f-ecdf2c06f444"
#define CXL_NAMESPACE_UUID "68bb2c0a-5a77-4937-9f85-3caf41a0f93c"
Here we are setting label->type with CXL_NAMESPACE_UUID
In following patch, accordingly we are setting region label->type with
CXL_REGION_UUID
May be I will rename it to nsl_set_type_uuid() in next patch-set.
>Why is driver data passed here?
ndd->cxl is used to segregate between EFI labels (v1.1 & v1.2) and CXL
Labels (v2.1). It was introduced in 5af96835e4daf
>
>This reads as an accessor function for some sort of label class but seems
>to do some back checking into ndd to set the uuid of the label?
>
>At a minimum this should be *_set_uuid(..., uuid_t uuid) But I'm not
>following this chunk of changes so don't just change it without more
>explaination.
I have created setter function taking inspiration from other members
setter helpers introduced in 8176f14789125
>
>> +{
>> + uuid_t tmp;
>> +
>> + if (ndd->cxl) {
>> + uuid_parse(CXL_NAMESPACE_UUID, &tmp);
>> + export_uuid(ns_label->cxl.type, &tmp);
>> + }
>> +}
>> +
>> +static inline void nsl_set_alignment(struct nvdimm_drvdata *ndd,
>> + struct nd_namespace_label *ns_label,
>> + u32 align)
>
>Why is this needed?
As per CXL spec 3.2 Table - 9-11. Namespace Label Layout
The desired region alignment in multiples of 256 MB:
• 0 = No desired alignment
• 1 = 256-MB desired alignment
• 2 = 512-MB desired alignment
• etc.
In this patch-set we are using 0.
>
>> +{
>> + if (ndd->cxl)
>> + ns_label->cxl.align = __cpu_to_le16(align);
>> +}
>> +
>> +static inline void nsl_set_region_uuid(struct nvdimm_drvdata *ndd,
>> + struct nd_namespace_label *ns_label,
>> + const uuid_t *uuid)
>
>Again why?
This field is used to track namespace label associated with perticular
region label. It stores the region label's UUID
>
>> +{
>> + if (ndd->cxl)
>> + export_uuid(ns_label->cxl.region_uuid, uuid);
>
>export does a memcpy() and you are passing it NULL. Is that safe?
>
>Ira
Thanks Ira for pointing this, Yes it will not be safe with NULL.
Sure I will fix this in next patch-set.
Regards,
Neeraj
[-- Attachment #2: Type: text/plain, Size: 0 bytes --]
next prev parent reply other threads:[~2025-09-05 7:03 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250730121221epcas5p3ffb9e643af6b8ae07cfccf0bdee90e37@epcas5p3.samsung.com>
2025-07-30 12:11 ` [PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 01/20] nvdimm/label: Introduce NDD_CXL_LABEL flag to set cxl label format Neeraj Kumar
2025-08-13 13:12 ` Jonathan Cameron
2025-08-15 18:06 ` Dave Jiang
2025-09-04 13:24 ` Neeraj Kumar
2025-09-04 13:20 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 02/20] nvdimm/label: Prep patch to accommodate cxl lsa 2.1 support Neeraj Kumar
2025-08-13 13:23 ` Jonathan Cameron
2025-09-04 13:27 ` Neeraj Kumar
2025-08-15 22:02 ` Dave Jiang
2025-09-04 13:31 ` Neeraj Kumar
2025-08-18 21:48 ` Dave Jiang
2025-09-04 13:33 ` Neeraj Kumar
2025-08-19 15:38 ` Ira Weiny
2025-09-04 13:42 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 03/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
2025-07-31 13:12 ` kernel test robot
2025-08-13 13:27 ` Jonathan Cameron
2025-09-04 13:40 ` Neeraj Kumar
2025-08-19 15:57 ` Ira Weiny
2025-09-04 13:51 ` Neeraj Kumar [this message]
2025-08-19 19:36 ` Ira Weiny
2025-09-05 5:34 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 04/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
2025-08-13 13:44 ` Jonathan Cameron
2025-09-04 13:54 ` Neeraj Kumar
2025-08-15 21:02 ` Dave Jiang
2025-09-04 14:01 ` Neeraj Kumar
2025-08-19 16:04 ` Ira Weiny
2025-09-04 14:02 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 05/20] nvdimm/region_label: Add region label updation routine Neeraj Kumar
2025-07-31 15:07 ` kernel test robot
2025-08-13 14:48 ` Jonathan Cameron
2025-09-04 14:06 ` Neeraj Kumar
2025-08-15 21:55 ` Dave Jiang
2025-09-04 14:12 ` Neeraj Kumar
2025-09-10 14:03 ` Jonathan Cameron
2025-08-15 23:12 ` Dave Jiang
2025-09-04 14:13 ` Neeraj Kumar
2025-08-19 18:16 ` Ira Weiny
2025-09-04 14:18 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 06/20] nvdimm/region_label: Add region label deletion routine Neeraj Kumar
2025-08-13 14:53 ` Jonathan Cameron
2025-09-04 14:20 ` Neeraj Kumar
2025-08-15 22:22 ` Dave Jiang
2025-09-04 14:23 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 07/20] nvdimm/namespace_label: Update namespace init_labels and its region_uuid Neeraj Kumar
2025-08-13 14:58 ` Jonathan Cameron
2025-09-04 14:24 ` Neeraj Kumar
2025-08-19 18:56 ` Ira Weiny
2025-09-04 14:28 ` Neeraj Kumar
2025-09-05 20:08 ` Ira Weiny
2025-09-08 5:36 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-08-13 15:07 ` Jonathan Cameron
2025-09-04 14:30 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
2025-08-13 15:09 ` Jonathan Cameron
2025-09-04 14:31 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 10/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
2025-08-13 15:11 ` Jonathan Cameron
2025-09-04 14:33 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 11/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
2025-08-13 15:13 ` Jonathan Cameron
2025-07-30 12:12 ` [PATCH V2 12/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-08-13 15:55 ` Jonathan Cameron
2025-09-04 14:34 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-08-20 16:41 ` Dave Jiang
2025-09-04 14:39 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation Neeraj Kumar
2025-08-20 0:30 ` Dave Jiang
2025-09-04 14:55 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 15/20] cxl: Add a routine to find cxl root decoder on cxl bus using cxl port Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 18/20] cxl/pmem: Add support of cxl lsa 2.1 support in cxl pmem Neeraj Kumar
2025-07-31 1:36 ` kernel test robot
2025-07-30 12:12 ` [PATCH V2 19/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-07-31 1:57 ` kernel test robot
2025-07-31 2:17 ` kernel test robot
2025-07-30 12:12 ` [PATCH V2 20/20] cxl/pmem_region: Add sysfs attribute cxl region label updation/deletion Neeraj Kumar
2025-07-31 10:36 ` kernel test robot
2025-08-07 9:02 ` [PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-08-12 21:46 ` Dave Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1983025922.01757055782611.JavaMail.epsvc@epcpadp2new \
--to=s.neeraj@samsung.com \
--cc=a.manzanares@samsung.com \
--cc=cpgs@samsung.com \
--cc=gost.dev@samsung.com \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=neeraj.kernel@gmail.com \
--cc=nvdimm@lists.linux.dev \
--cc=vishak.g@samsung.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.