--- head.S	Thu Jul  9 19:51:48 1998
+++ sgi-lin/linux/arch/mips/kernel/head.S	Tue Aug 18 22:34:35 1998
@@ -5,6 +5,7 @@
  *  Copyright (C) 1996, 1997, 1998 Ralf Baechle
  *  Modified for DECStation and hence R3000 support by Paul M. Antoine
  *  Further modifications by David S. Miller
+ *  Modified for R4000SC/R44000SC support by Ulf Carlsson
  *
  *  Head.S contains the MIPS exception handler and startup code.
  */
@@ -22,6 +23,7 @@
 #include <asm/stackframe.h>
 #include <asm/bootinfo.h>
 #include <asm/cpu.h>
+#include <asm/cacheops.h>
 
 	.text
 	/*
@@ -315,16 +317,46 @@
 	NESTED(except_vec3_r4000, 0, sp)
 	.set	noat
 	mfc0	k1, CP0_CAUSE
-
-	/* XXX Have to check for VCE's _before_ we do a load or store. */
-
-	la	k0, exception_handlers
 	andi	k1, k1, 0x7c
+	li	k0, 31<<2
+	beq	k1, k0, handle_vced
+	 li	k0, 14<<2
+	beq	k1, k0, handle_vcei
+	 la	k0, exception_handlers
 	addu	k0, k0, k1
 	lw	k0, (k0)
 	nop
 	jr	k0
 	 nop
+
+/*
+ * Big shit, we now may have two dirty primary cache lines for the same
+ * physical address.  We can savely invalidate the line pointed to by
+ * c0_badvaddr because after return from this exception handler the load /
+ * store will be re-executed.
+ *
+ * XXX should bitch on console.
+ */
+handle_vced:
+	mfc0	k0, CP0_BADVADDR
+	mtc0	zero, CP0_TAGLO
+	nop;nop
+	cache	Index_Store_Tag_D,(k0)
+	nop;nop
+	cache	Hit_Writeback_Inv_SD,(k0)
+	eret
+
+/*
+ * VCEI is simpler and should never happen unless userland is doing something
+ * really stupid.  It's actually worth a SIGFRY.
+ *
+ * XXX should bitch on console.
+ */
+handle_vcei:
+	mfc0	k0, CP0_BADVADDR
+	cache	Hit_Invalidate_SD,(k0)		# also cleans pi
+	eret
+
 	END(except_vec3_r4000)
 	.set	at