Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Bjorn Helgaas <helgaas@rsn.hp.com>]

>	Exact form of these tables is s/w convention. 
>
>Q.	If the format is software convention, does that mean
>	the fields within TLB slots are not defined by Hardware ?

There is no architectural definition of hardware TLB miss handling,
and most PA-RISC processors do not implement it.

On the ones that do support hardware TLB miss handling, the hardware
expects a certain format, and it is essentially the one given in the
examples in the architecture books.  The hardware TLB walker expects
a hash table of PDIR entries (indexed by a function of the space and
offset), and it only looks at the entries in the table.  Hash collisions
are resolved by a linked list, and the hardware does not walk the list;
this is left for the software miss handler.