Question about SMP

Question about SMP

[Brad Boyer]

I've been trying to get SMP working on my PowerMac for some time now,
and it just never seems to work.  I've tried compiling my own kernels,
as well as compiling my own, and I've never had a working SMP system.
I just tried to compile a 2.2.7 kernel from the rsync code on
samba.anu.edu.au and got a better result than I have in a while, but
still not good.  It starts up fine, but then fails as soon as it has
to start using the scheduler.  It prints out the first line in
rc.sysinit, which is the comment about starting swap, tries to run
swapon, and then just starts printing messages to the console about
spin_lock and write_lock, I believe it was.  I wrote down the
addresses it had in the errors, and looked them up in the System.map.
The first one was in schedule() with a pointer to scheduler_lock, and
the other one only gave a pointer, which was waitqueue_lock.

I started looking at kernel/sched.c which is where most of this stuff
is, and I didn't see anything obvious, but I did notice a few things
that seemed odd.  Do spinlocks only exist in an SMP kernel?  I ask
because there is a spinlock where the matching unlock is in an #ifdef
__SMP__ which seemed like a bad idea.  If anyone can help me get this
running, I'd appreciate it.  I'm more than willing to fiddle around
with the code if someone can give me some hints on this stuff.

	 Brad Boyer
	 flar@cegt201.bradley.edu

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Re: Question about SMP

[Charles E. Leiserson, Jr.]

What model PowerMac do you have?

I have a 2.2.7 kernel that runs very nicely on a PowerMac 7300/400MP.  It's been tried by several others on different machines, and it has worked.

You can find it at ftp://borg.mit.edu/pub/linux/ppc/kernels/multiprocessor/ along with its various support files (ie. System.map, modules, .config, etc.).  They're all gzipped and ready to use.  Don't forget to untar modules.tar.gz from / :)

If it works, you can compile your own from the .config file provided.  Good luck!


					- Ricky

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Re: Question about SMP

[Sriranga Veeraraghavan]

> I started looking at kernel/sched.c which is where most of this stuff
> is, and I didn't see anything obvious, but I did notice a few things
> that seemed odd.  Do spinlocks only exist in an SMP kernel?  I ask
> because there is a spinlock where the matching unlock is in an #ifdef
> __SMP__ which seemed like a bad idea.  If anyone can help me get this
> running, I'd appreciate it.  I'm more than willing to fiddle around
> with the code if someone can give me some hints on this stuff.
 
My knowledge of SMP is limited, but in general spin locks are required
only on MP machines.  If you use a spin lock (condition variable?) on
a single processor machine, basically your thread ends up spinning
until its time slice runs out, which is not particularly efficient.

I think that on single processors locks are implemented using sem_wait
and sem_post, where these enable and disable interrupts. This is not
possible on MP machines, so spin locks are used instead. (Someone
please correct me if I'm wrong).

>From you post, I take it that my SMP kernel didn't work for you. What
was the exact problem you had?

----ranga <ranga@soda.berkeley.edu>

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Re: Question about SMP

[Brad Boyer]

> >From you post, I take it that my SMP kernel didn't work for you. What
> was the exact problem you had?

Well, the 2.2.0pre6 kernel I downloaded didn't even boot.  Not from OF
when I downloaded it in Linux, and not from BootX when I downloaded it
in the MacOS.  And I downloaded different ones each time, to get the
appropriate compression for the OS.  In BootX, it just printed the
"Welcome to Linux" line and hung.  It didn't do much better in OF, as
I recall.  I also downloaded a 2.2.7 kernel from someone at MIT who
gave me a URL, but while it worked better, it still wasn't actually
useable.  It did the same thing as the one I compiled from the 2.2.7
source.  It did all the initial stuff, started init, printed the
message about swap, and then started printing the spinlock errors.  I
hope someone has some idea what's happening here.  I know my second
processor works, because I've used it in the MacOS and BeOS...

		 Brad Boyer
		 flar@cegt201.bradley.edu

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LinuxPPC/iMac instabilities

[Derek Moeller]

	I've been having instabilities with the installation on the
iMac<RevA>. It has been persistent since the beginning of installation,
and can force me to do a reboot as much as once a day. Other that that, it
has been very stable.
	The particulars of the problem: When switching between VCs (ie
cmd-F1) it will sometimes, after the screen clear, print "FB: Overflow
xxx" where xxx is a number that increments rapidly with slowing speed as
time progresses. This isn't FBDev since it's on the console, not X. Has
anyone else experience this problem under the iMac? I use the boot
commands of video=atyfb:vmode:17,cmode:16 . I would like to know whether
I'm experiencing an isolated incident, whether a fix is forthcoming, or
whether it's already been fixed.
	Some more info: it overflows after a period of time. For example,
I left the machine on for awhile, and when coming back to it it took less
than 5 minutes for it to give me the Overflow stuff. Installation is R4.1
CD. I've tried to be good at giving as much info, if I've missed something
(probably have) ask. Oh, also - it _never_ happens unless I am actively
switching VCs.
	Thank you in advance!

--

+----------------------------------------+
| Derek Moeller moeller@networksplus.net |
|     Linux for PowerPC User, Student    |
|   http://www.networksplus.net/moeller	 |
|	*	   *		*	 |
|    "aut inveniam viam aut faciam"	 |
+----------------------------------------+

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Question about SMP

[Dave Hylands]

Hi,

(filled in subject line this time - Doh).

I'm trying to understand what I need to be concerned about with SMP
processors and sharing global data (in particular a dual Cortex-A9)

I'm familiar with spinlocks, but in this case I'm trying to work with
some lockless data structures.

What I'm not sure is whether the following would work. Suppose I have
a couple of 8-bit get/put indicies which are in adjacent memory
locations (within the same 32-bit word).

If I have an ISR and a thread running on an SMP core, and the ISR is
running on one core and the thread is running on a second core, if the
ISR were to only write to the put pointer and the thread were only to
write to the get pointer, does the cache maintain consistency? Or do
the get and put pointers need to be in separate cache lines?

Another way of asking this: If both cores are writing to the same
32-bit word (but different bytes) do the writes collide?

--
Dave Hylands
Shuswap, BC, Canada
http://www.DaveHylands.com/

Question about SMP

[Catalin Marinas]

On Mon, 2010-06-07 at 21:11 +0100, Dave Hylands wrote:
> I'm trying to understand what I need to be concerned about with SMP
> processors and sharing global data (in particular a dual Cortex-A9)
> 
> I'm familiar with spinlocks, but in this case I'm trying to work with
> some lockless data structures.

You should be really concerned about memory ordering and barriers :).
See Documentation/memory-barriers.txt in the kernel source.

> What I'm not sure is whether the following would work. Suppose I have
> a couple of 8-bit get/put indicies which are in adjacent memory
> locations (within the same 32-bit word).
> 
> If I have an ISR and a thread running on an SMP core, and the ISR is
> running on one core and the thread is running on a second core, if the
> ISR were to only write to the put pointer and the thread were only to
> write to the get pointer, does the cache maintain consistency? Or do
> the get and put pointers need to be in separate cache lines?

The consistency is maintained (though be careful about memory ordering
and when the put/get pointers become visible to the other CPUs).

> Another way of asking this: If both cores are writing to the same
> 32-bit word (but different bytes) do the writes collide?

No, though it's not very efficient because of cache line being moved
between CPUs. See http://en.wikipedia.org/wiki/MESI_protocol.

-- 
Catalin