From: Tom Vier <thomassr@erols.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linuxppc-dev@lists.linuxppc.org
Subject: Re: question about altivec registers
Date: Tue, 26 Oct 1999 18:38:26 -0400 [thread overview]
Message-ID: <19991026183826.A6668@zero> (raw)
In-Reply-To: <Pine.LNX.4.05.9910262020350.665-100000@callisto.of.borg>
On Tue, Oct 26, 1999 at 08:22:06PM +0200, Geert Uytterhoeven wrote:
> Moving around blocks of 512 bytes quickly thrashes the L1 cache, unless the
> loads/stores are done using cache-bypassing instructions (cfr. MOVE16 on '040).
> Don't know whether PPC has these (still no PPC guru :-(
from what i've read, you can disable cache for the altivec regs. this was
intended for doing infrequent vector ops between frequent vectors ops
(loops) without distrubing the cache.
--
Tom Vier - 0x27371A1C
thomassr@erols.com
http://users.erols.com/thomassr/zero/
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next prev parent reply other threads:[~1999-10-26 22:38 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-10-25 20:51 question about altivec registers Jim Terman
1999-10-25 22:27 ` Claude Robitaille
1999-10-25 22:31 ` Jim Terman
1999-10-25 22:44 ` erik cameron
1999-10-25 23:28 ` Claude Robitaille
[not found] ` <Pine.LNX.4.10.9910251916060.5902-100000@modemcable220.93-200-24.mtl.mc.vi deotron.net>
1999-10-25 23:53 ` Rob Barris
1999-10-26 18:22 ` Geert Uytterhoeven
1999-10-26 22:13 ` Rob Barris
1999-10-26 22:38 ` Tom Vier [this message]
1999-10-26 22:03 ` Tom Vier
1999-10-26 4:42 ` Kumar Gala
1999-10-26 21:52 ` Jim Terman
1999-10-26 22:43 ` Kumar Gala
1999-10-27 8:58 ` Adrian Cox
1999-10-27 13:21 ` Gabriel Paubert
1999-10-27 16:05 ` Geert Uytterhoeven
1999-10-27 18:23 ` Kumar Gala
1999-10-27 22:39 ` Tony Mantler
1999-10-28 11:01 ` Gabriel Paubert
1999-10-28 21:20 ` Tony Mantler
1999-10-29 11:58 ` Benjamin Herrenschmidt
1999-10-29 12:49 ` Gabriel Paubert
1999-10-30 4:14 ` Tony Mantler
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