From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21CABC54798 for ; Tue, 5 Mar 2024 10:25:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.688714.1073180 (Exim 4.92) (envelope-from ) id 1rhRyt-0006Si-Q3; Tue, 05 Mar 2024 10:25:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 688714.1073180; Tue, 05 Mar 2024 10:25:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rhRyt-0006Sb-N1; Tue, 05 Mar 2024 10:25:07 +0000 Received: by outflank-mailman (input) for mailman id 688714; Tue, 05 Mar 2024 10:25:06 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rhRys-0005r6-Kc for xen-devel@lists.xenproject.org; Tue, 05 Mar 2024 10:25:06 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a27634e0-dada-11ee-afda-a90da7624cb6; Tue, 05 Mar 2024 11:25:06 +0100 (CET) Received: from support.bugseng.com (support.bugseng.com [162.55.131.47]) by support.bugseng.com (Postfix) with ESMTPA id BDBB54EE0737; Tue, 5 Mar 2024 11:25:05 +0100 (CET) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a27634e0-dada-11ee-afda-a90da7624cb6 MIME-Version: 1.0 Date: Tue, 05 Mar 2024 11:25:05 +0100 From: Nicola Vetrini To: Stefano Stabellini Cc: Julien Grall , Bertrand Marquis , Michal Orzel , xenia.ragiadakou@amd.com, ayan.kumar.halder@amd.com, consulting@bugseng.com, andrew.cooper3@citrix.com, roger.pau@citrix.com, Volodymyr Babchuk , xen-devel@lists.xenproject.org Subject: Re: [XEN PATCH 02/10] xen/arm: address some violations of MISRA C Rule 20.7 In-Reply-To: References: <905119be-8731-4669-ac7f-c21aed6845dc@suse.com> <7c54b08875406e5b3a61325af124ae7f@bugseng.com> <0aae1c64587cfbc67e81a20b36dd5056@bugseng.com> Message-ID: <1a53d19ab3d901ce82ce391606ffef92@bugseng.com> X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit On 2024-03-05 02:43, Stefano Stabellini wrote: > On Mon, 4 Mar 2024, Nicola Vetrini wrote: >> Hi, >> >> as the maintainers of this subsystem, would you prefer Jan's version >> or the >> one in the patch? >> Both are fine w.r.t MISRA Rule 20.7 because the macro arguments >> themselves are >> parenthesized. > > I prefer Jan's version. Thanks for asking Nicola. > Ok, thanks. I'll modify it and keep an eye for possibly additional opinions of other maintainers. > >> > > > --- a/xen/arch/arm/include/asm/vgic-emul.h >> > > > +++ b/xen/arch/arm/include/asm/vgic-emul.h >> > > > @@ -6,11 +6,11 @@ >> > > > * a range of registers >> > > > */ >> > > > >> > > > -#define VREG32(reg) reg ... reg + 3 >> > > > -#define VREG64(reg) reg ... reg + 7 >> > > > +#define VREG32(reg) (reg) ... (reg) + 3 >> > > > +#define VREG64(reg) (reg) ... (reg) + 7 >> > > >> > > #define VREG32(reg) (reg) ... ((reg) + 3) >> > > #define VREG64(reg) (reg) ... ((reg) + 7) >> > > >> > > ? >> > > >> > >> > The outer parentheses are not required, but I can add them if the >> > maintainers share your view. -- Nicola Vetrini, BSc Software Engineer, BUGSENG srl (https://bugseng.com)