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>> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter), >> + "Poison error detected\n"); >> break; >> case XE_RAS_MEMORY_DATA_PARITY: >> - xe_info(xe, "[RAS]: Data parity error detected\n"); >> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter), >> + "Data parity error detected\n"); >> break; >> case XE_RAS_MEMORY_DB_ECC: >> - xe_info(xe, "[RAS]: Double-bit ECC error detected at sw address 0x%llx\n", >> - info->sw_address); >> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter), >> + "Double-bit ECC error detected at sw address 0x%llx\n", >> + info->sw_address); > [Severity: Medium] > Will this incorrectly report double-bit ECC memory errors with > CPER_SEV_INFORMATIONAL severity despite being severe enough to trigger a > device reset? > > The xe_log_comp_info macro hardcodes the CPER severity to > CPER_SEV_INFORMATIONAL. After logging, the switch statement falls through > to the default case and returns XE_RAS_RECOVERY_ACTION_RESET. > > Could this break automated fleet management that acts on CPER severities > because a severe uncorrectable double-bit ECC error is logged as > informational while the driver actually resets the GPU? These were already logged at info level; this patch only converts them to xe_log_* without changing the level. Aligning the CPER severity with the counter severity for memory errors can be done as a follow-up. Thanks, Badal