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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>,
	Ross Lagerwall <ross.lagerwall@citrix.com>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Roger Pau Monné" <roger@xenproject.org>,
	"Jason Andryuk" <jason.andryuk@amd.com>,
	"Teddy Astie" <teddy.astie@vates.tech>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1] x86/svm: Intercept CR0 writes selectively
Date: Thu, 3 Sep 2026 15:31:53 +0100	[thread overview]
Message-ID: <1acb3901-c159-49c5-bd59-aa7be58c67cb@citrix.com> (raw)
In-Reply-To: <6ecdf1d1-784e-4cc0-b840-f8970a295ed5@citrix.com>

On 03/09/2026 3:31 pm, Andrew Cooper wrote:
> On 03/09/2026 2:02 pm, Jan Beulich wrote:
>>> Aside from potentially reducing a few
>>> VMEXITs, this fixes a nested virt bug where L1 intercepts CR0_SEL_WRITE
>>> and L0 intercepts CR0_WRITE. The hardware prioritizes CR0_WRITE and so
>>> L1 never sees any CR0 writes.
>> Yet if L1 sets CR0_WRITE, since intercept masks are ORed together (if
>> I'm not mistaken),
> L0's choice of intercepts needs combining with L1's choice of intercepts.
>
> Mostly this is OR-ing/unioning, but not exclusively, just like levelling
> for migrate isn't a straight interception.

Sorry, intersection.

~Andrew


      reply	other threads:[~2026-09-03 14:32 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-28 14:19 [PATCH v1] x86/svm: Intercept CR0 writes selectively Ross Lagerwall
2026-09-03 13:02 ` Jan Beulich
2026-09-03 13:35   ` Ross Lagerwall
2026-09-03 13:48     ` Jan Beulich
2026-09-03 14:31   ` Andrew Cooper
2026-09-03 14:31     ` Andrew Cooper [this message]

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