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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <583b0a190bad7121eae9bc99bd1e13dc1743efe4.1787838835.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1788877011-F1CAA2AC-CD9490D3/0/0 X-purgate-type: clean X-purgate-size: 2882 On 27.08.2026 17:21, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/riscv_encoding.h > +++ b/xen/arch/riscv/include/asm/riscv_encoding.h > @@ -109,6 +109,12 @@ > #define SIP_SSIP MIP_SSIP > #define SIP_STIP MIP_STIP > > +/* stvec/vstvec: MODE is bits [1:0], BASE is bits [XLEN-1:2] */ > +#define STVEC_MODE_MASK _UL(0x3) > +#define STVEC_MODE_DIRECT _UL(0x0) > +#define STVEC_MODE_VECTORED _UL(0x1) As on earlier occasions: Do the 0x here actually add any value? There are none ... > +#define STVEC_BASE_MASK (~STVEC_MODE_MASK) > + > #define PRV_U _UL(0) > #define PRV_S _UL(1) > #define PRV_M _UL(3) ... here, for example. > --- a/xen/arch/riscv/traps.c > +++ b/xen/arch/riscv/traps.c > @@ -294,5 +294,53 @@ enum mc_disposition arch_do_multicall_call(struct mc_state *state) > /* Redirect trap to Guest. */ > void trap_redirect(const struct trap_info *trap) > { > - BUG_ON("unimplemented"); > + struct cpu_user_regs *regs = vcpu_guest_cpu_user_regs(current); > + unsigned long vsstatus = csr_read(CSR_VSSTATUS); > + > + /* > + * Redirecting a trap makes sense only if the trap was taken from > + * virtualized mode, i.e. sret is going to return to VS-mode. > + */ > + ASSERT(regs->hstatus & HSTATUS_SPV); > + > + /* > + * Only synchronous exceptions can be redirected. Interrupts must be > + * injected via hvip instead, so that the hardware itself performs > + * VS-mode trap entry, respecting vsstatus.SIE and the vectored > + * dispatch (BASE + 4 * cause) if vstvec is configured so. > + */ > + ASSERT(!(trap->scause & CAUSE_IRQ_FLAG)); > + > + /* Change Guest SSTATUS.SPP bit */ > + vsstatus &= ~SSTATUS_SPP; > + if ( regs->sstatus & SSTATUS_SPP ) > + vsstatus |= SSTATUS_SPP; > + > + /* Change Guest SSTATUS.SPIE bit */ > + vsstatus &= ~SSTATUS_SPIE; > + if ( vsstatus & SSTATUS_SIE ) > + vsstatus |= SSTATUS_SPIE; > + > + /* Clear Guest SSTATUS.SIE bit */ > + vsstatus &= ~SSTATUS_SIE; > + > + /* Update Guest SSTATUS */ > + csr_write(CSR_VSSTATUS, vsstatus); > + > + /* Update Guest SCAUSE, STVAL, and SEPC */ > + csr_write(CSR_VSCAUSE, trap->scause); > + csr_write(CSR_VSTVAL, trap->stval); > + csr_write(CSR_VSEPC, trap->sepc); > + > + /* > + * Set Guest PC to Guest exception vector. > + * > + * vstvec's MODE field is not part of the address. Exceptions always > + * target BASE regardless of MODE, so mask it off explicitly instead of > + * relying on the hardwired zero bit of sepc to drop it. > + */ > + regs->sepc = csr_read(CSR_VSTVEC) & STVEC_BASE_MASK; Nit: Given how much the comment talks about MODE, imo using ~STVEC_MODE_MASK here directly (and dropping STVEC_BASE_MASK) might be better. Jan