From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"Bob Eshleman" <bobbyeshleman@gmail.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Stefano Stabellini" <sstabellini@kernel.org>,
"Romain Caritey" <Romain.Caritey@microchip.com>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v6 1/7] xen/riscv: imsic_init() implementation
Date: Thu, 10 Jul 2025 12:47:50 +0200 [thread overview]
Message-ID: <1b95d8b4-2d44-484b-a3f2-5952bb37cfcb@gmail.com> (raw)
In-Reply-To: <607f9a3a-6a70-4a9b-9bb0-65138b49b6ae@suse.com>
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On 7/8/25 3:52 PM, Jan Beulich wrote:
> On 07.07.2025 11:01, Oleksii Kurochko wrote:
>> imsic_init() is introduced to parse device tree node, which has the following
>> bindings [2], and based on the parsed information update IMSIC configuration
>> which is stored in imsic_cfg.
>>
>> The following helpers are introduces for imsic_init() usage:
>> - imsic_parse_node() parses IMSIC node from DTS
>> - imsic_get_parent_hartid() returns the hart ( CPU ) ID of the given device
>> tree node.
>>
>> This patch is based on the code from [1].
>>
>> Since Microchip originally developed imsic.{c,h}, an internal discussion with
>> them led to the decision to use the MIT license.
>>
>> [1]https://gitlab.com/xen-project/people/olkur/xen/-/commit/0b1a94f2bc3bb1a81cd26bb75f0bf578f84cb4d4
>> [2]https://elixir.bootlin.com/linux/v6.12/source/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
>>
>> Co-developed-by: Romain Caritey<Romain.Caritey@microchip.com>
>> Signed-off-by: Oleksii Kurochko<oleksii.kurochko@gmail.com>
> Acked-by: Jan Beulich <jbeulich@suse.com
>
> I'm curious though:
>
>> --- a/xen/arch/riscv/include/asm/smp.h
>> +++ b/xen/arch/riscv/include/asm/smp.h
>> @@ -3,6 +3,7 @@
>> #define ASM__RISCV__SMP_H
>>
>> #include <xen/cpumask.h>
>> +#include <xen/macros.h>
>> #include <xen/percpu.h>
>>
>> #include <asm/current.h>
>> @@ -18,6 +19,18 @@ static inline unsigned long cpuid_to_hartid(unsigned long cpuid)
>> return pcpu_info[cpuid].hart_id;
>> }
>>
>> +static inline unsigned int hartid_to_cpuid(unsigned long hartid)
>> +{
>> + for ( unsigned int cpu = 0; cpu < ARRAY_SIZE(pcpu_info); cpu++ )
>> + {
>> + if ( hartid == cpuid_to_hartid(cpu) )
>> + return cpu;
>> + }
>> +
>> + /* hartid isn't valid for some reason */
>> + return NR_CPUS;
>> +}
> Since there's no FIXME or alike here, is this really intended to remain this
> way? With many CPUs this form of lookup can be pretty inefficient.
In the case with a big amount of CPUs it will require to update it. I will create
TODO task in my repo to not forget to update it in a future.
Thanks.
~ Oleksii
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next prev parent reply other threads:[~2025-07-10 10:48 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-07 9:01 [PATCH v6 0/7] riscv: introduce basic UART support and interrupts for hypervisor mode Oleksii Kurochko
2025-07-07 9:01 ` [PATCH v6 1/7] xen/riscv: imsic_init() implementation Oleksii Kurochko
2025-07-08 13:52 ` Jan Beulich
2025-07-10 10:47 ` Oleksii Kurochko [this message]
2025-07-07 9:01 ` [PATCH v6 2/7] xen/riscv: aplic_init() implementation Oleksii Kurochko
2025-07-08 13:58 ` Jan Beulich
2025-07-10 11:19 ` Oleksii Kurochko
2025-07-10 11:29 ` Jan Beulich
2025-07-10 11:56 ` Jan Beulich
2025-07-07 9:01 ` [PATCH v6 3/7] xen/riscv: introduce intc_init() and helpers Oleksii Kurochko
2025-07-07 9:01 ` [PATCH v6 4/7] xen/riscv: implementation of aplic and imsic operations Oleksii Kurochko
2025-07-07 9:01 ` [PATCH v6 5/7] xen/riscv: add external interrupt handling for hypervisor mode Oleksii Kurochko
2025-07-07 9:01 ` [PATCH v6 6/7] xen/riscv: implement setup_irq() Oleksii Kurochko
2025-07-07 9:01 ` [PATCH v6 7/7] xen/riscv: add basic UART support Oleksii Kurochko
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