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X-CSE-ConnectionGUID: K6zbf8Z9Svmddakxi9f94A== X-CSE-MsgGUID: TvuKCzdmRGiLddiDfBHnrg== X-IronPort-AV: E=McAfee;i="6800,10657,11892"; a="92478635" X-IronPort-AV: E=Sophos;i="6.25,255,1779174000"; d="scan'208";a="92478635" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 23:57:41 -0700 X-CSE-ConnectionGUID: yz/vJrMBQGCnikgHJg6cFw== X-CSE-MsgGUID: xKD0Q0N2TC6Z5ccIo5lu/g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,255,1779174000"; d="scan'208";a="298899397" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.241.239]) ([10.124.241.239]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 23:57:36 -0700 Message-ID: <1bc5d41b-103f-46ba-bcb6-bac930014030@linux.intel.com> Date: Tue, 1 Sep 2026 14:57:35 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 13/16] KVM: x86/pmu: Factor out fixed counter control bit calculation To: Zide Chen , Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Andi Kleen , Jim Mattson , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Das Sandipan , Shukla Manali , Xudong Hao References: <20260827223755.143247-1-zide.chen@intel.com> <20260827223755.143247-14-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260827223755.143247-14-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reviewed-by: Dapeng Mi On 8/28/2026 6:37 AM, Zide Chen wrote: > Rename intel_pmu_enable_fixed_counter_bits() to > intel_pmu_fixed_ctrl_bits() and have it return the computed fixed > counter control mask instead of updating fixed_ctr_ctrl_rsvd directly. > > Accumulate the desired fixed counter control bits during PMU setup and > apply them once in intel_pmu_refresh(). > > Move the helper next to intel_pmu_set_msr() so it can also be reused > there, which will be needed for upcoming ANYTHREAD_DEPRECATION > emulation. > > No functional change intended. > > Signed-off-by: Zide Chen > --- > v2: New patch > --- > arch/x86/kvm/vmx/pmu_intel.c | 32 +++++++++++++++++++------------- > 1 file changed, 19 insertions(+), 13 deletions(-) > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index 1ce69e764ae1..c7472778137a 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -421,6 +421,18 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > return 0; > } > > +static u64 intel_pmu_fixed_ctrl_bits(struct kvm_pmu *pmu, u64 bits) > +{ > + unsigned long fixed_mask = kvm_fixed_pmc_mask(pmu); > + u64 fixed_ctrl_bits = 0; > + int i; > + > + kvm_for_each_fixed_counter(i, fixed_mask) > + fixed_ctrl_bits |= intel_fixed_bits_by_idx(i, bits); > + > + return fixed_ctrl_bits; > +} > + > static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > { > struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); > @@ -533,20 +545,12 @@ static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index) > return eventsel; > } > > -static void intel_pmu_enable_fixed_counter_bits(struct kvm_pmu *pmu, u64 bits) > -{ > - unsigned long fixed_mask = kvm_fixed_pmc_mask(pmu); > - int i; > - > - kvm_for_each_fixed_counter(i, fixed_mask) > - pmu->fixed_ctr_ctrl_rsvd &= ~intel_fixed_bits_by_idx(i, bits); > -} > - > static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > { > struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); > struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); > struct kvm_cpuid_entry2 *entry; > + u64 fixed_enable_bits = 0; > union cpuid10_eax eax; > union cpuid10_edx edx; > u64 perf_capabilities; > @@ -625,9 +629,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > kvm_pmu_cap.bit_width_fixed); > pmu->counter_bitmask[KVM_PMC_FIXED] = BIT_ULL(edx.split.bit_width_fixed) - 1; > > - intel_pmu_enable_fixed_counter_bits(pmu, INTEL_FIXED_0_KERNEL | > - INTEL_FIXED_0_USER | > - INTEL_FIXED_0_ENABLE_PMI); > + fixed_enable_bits |= INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | > + INTEL_FIXED_0_ENABLE_PMI; > > counter_rsvd = ~(kvm_gp_pmc_mask(pmu) | > ((u64)kvm_fixed_pmc_mask(pmu) << KVM_FIXED_PMC_BASE_IDX)); > @@ -651,11 +654,14 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > pmu->pebs_enable_rsvd = counter_rsvd; > pmu->eventsel_rsvd &= ~ICL_EVENTSEL_ADAPTIVE; > pmu->pebs_data_cfg_rsvd = ~0xff00000full; > - intel_pmu_enable_fixed_counter_bits(pmu, ICL_FIXED_0_ADAPTIVE); > + fixed_enable_bits |= ICL_FIXED_0_ADAPTIVE; > } else { > pmu->pebs_enable_rsvd = ~kvm_gp_pmc_mask(pmu); > } > } > + > + pmu->fixed_ctr_ctrl_rsvd &= > + ~intel_pmu_fixed_ctrl_bits(pmu, fixed_enable_bits); > } > > static void intel_pmu_init(struct kvm_vcpu *vcpu)