Re: venus: encoder job execution hard-resets SoC on SM7325 (sc7280-compatible) — extensive analysis, need wrapper/GDSC insight

[Bryan O'Donoghue <bod@kernel.org>]

On 20/07/2026 21:41, Kirill Ermolitskiy wrote:
> Adapted Daniel's patch to kodiak: added the reserved-memory node with
> iommu-addresses covering [0, 0x25800000) for &venus plus a second
> memory-region entry. Since downstream yupik's non-secure pool is exactly
> 0x25800000-0xe0000000 and venus runs with a 32-bit DMA mask (top-down
> allocations land above 0xe0000000), I additionally reserved
> [0xe0000000, 4GiB). Both reservations confirmed via the iommu group's
> reserved_regions:
> 
> 0x0000000000000000 0x00000000257fffff reserved
> 0x00000000e0000000 0x00000000ffffffff reserved
> 
> Encoder still hard-resets identically at the first FTB. So on kodiak it
> doesn't look like an IOVA-window/SID issue — or at least not only that.
> 
> One more finding from diffing against downstream: mainline's
> sm7280_reg_preset zeroes the whole of 0xb0088 (AON region), while
> downstream applies it with mask 0x11, preserving the remaining bits. On
> this device the register holds 0x3 at core boot, so mainline does
> clobber a live bit. Preserving it (read-modify-write with downstream's
> mask) doesn't change the encoder outcome, but it's probably worth fixing
> regardless — same for video_cc_xo_clk, which downstream marks
> CLK_IS_CRITICAL and mainline videocc-sc7280 doesn't register at all
> (ported it, confirmed running at 19.2 MHz; no behavioral change either).
> 
> That exhausts what I can usefully test blind: DT constants (fw region,
> SMMU SID, CP ranges, clocks, GDSC offsets — all match downstream), power
> sequencing (hwmode / forced SW / GDSC always-on / legacy MMCC handshake /
> GDSC wait values), XO clock, max CX votes via required-opps, IOVA
> windows, two firmware stacks (old and coherent OS2.0.8.0 TZ+vpu pair),
> and both venus and iris — every variant that actually executes the
> encode engine resets the SoC at the first frame, silently, below the
> kernel (PSHOLD warm reset). Full two-sided HFI traces of healthy decode
> and dying encode sessions available; happy to test patches on hardware.

Eh it's not clear to me if you are running the venus or iris driver. 
Both are supported - can you flip the switch in your defconfig ?

Perhaps you are testing both already - if not please try the other driver.

---
bod