All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Kalra, Ashish" <ashish.kalra@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com,
	x86@kernel.org, hpa@zytor.com, seanjc@google.com,
	peterz@infradead.org, thomas.lendacky@amd.com,
	herbert@gondor.apana.org.au, davem@davemloft.net,
	ardb@kernel.org, pbonzini@redhat.com, aik@amd.com,
	Michael.Roth@amd.com, KPrateek.Nayak@amd.com,
	Tycho.Andersen@amd.com, Nathan.Fontenot@amd.com,
	ackerleytng@google.com, jackyli@google.com, pgonda@google.com,
	rientjes@google.com, jacobhxu@google.com, xin@zytor.com,
	pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com,
	dyoung@redhat.com, nikunj@amd.com, darwi@linutronix.de,
	linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
	kvm@vger.kernel.org, linux-coco@lists.linux.dev
Subject: Re: [PATCH v14 4/5] x86/sev: Perform RMP optimizations asynchronously
Date: Tue, 15 Sep 2026 16:04:31 -0500	[thread overview]
Message-ID: <1c3d9841-eef8-4c94-9b2c-a7ed92a68260@amd.com> (raw)
In-Reply-To: <20260914231546.GAaqiAIsjGUdsK3MAq@fat_crate.local>

Hello Boris,

On 9/14/2026 6:15 PM, Borislav Petkov wrote:
> On Mon, Sep 14, 2026 at 03:00:04PM -0500, Kalra, Ashish wrote:
>> Thanks, Boris. Splitting setup from start and collapsing to a single export makes sense — a couple of constraints from the RMPOPT
>> spec shape how it has to be done.
>>
>> RMPOPT_BASE can only be written (RMPOPT_EN set) when SYSCFG[SnpEn] and RMP_CFG[SegmentedRmpEn] are both 1; otherwise the access
>> #GP(0)s. So the MSR programming can't run from an init‑time initcall — SnpEn is 0 then and it would #GP. The software setup can,
>> though, so the split becomes:
>>
>>   - an initcall in this file does the software setup — allocate the workqueue and INIT_DELAYED_WORK(), no export;
>>   - snp_enable_rmpopt() (the single export) programs RMPOPT_BASE on the primary threads and queues the pass. ccp calls it after it
>>   has enabled SNP, and kvm‑amd calls it on teardown.
> 
> This programming sure sounds like something we don't need to repeat each time
> we enable RMPOPT...
> 
> rmpopt_pa_start is practically static so I'd love it if those MSRs are written
> once and that's it. The question is, do they keep their value when we disable
> SNP?
> 
> And I can basically imagine the answer from hw folks: "yeah, yeah, maybe, but
> to be on the safe side, you should always write them after having enabled
> SNP."
> 
> Because if not, I'd be perfectly fine with us setting them on the *first* SNP
> init and not touching them again.
> 
> IOW, this pseudo:
> 
> 	if (!rdmsr(RMPOPT_BASE))
> 		wrmsr(RMPOPT_BASE, ...):
> 
> This should probably be in the snp_enable_rmpopt() function anyway as it
> should do what we want.
> 
>> The same spec text makes that single entry point safe to call repeatedly: RMPOPT_BASE_ADDR is read‑only once RMPOPT_EN is 1 (and
>> RMPOPT_EN can't be cleared while SnpEn is 1), so a later call's write is a probably a no‑op rather than a reprogram. If we want
>> to avoid even the redundant IPIs, snp_enable_rmpopt() can read RMPOPT_BASE and skip programming when RMPOPT_EN is already set — a
>> hardware‑state check instead of an if (rmpopt_wq).
> 
> Yap, or that. Sounds ok to me if it works.
> 
>> On clearing X86_FEATURE_RMPOPT when the allocation fails: that hits the problem we ran into in earlier revisions — the workqueue
>> allocation is at initcall time, after alternatives are patched, where setup_clear_cpu_cap() isn't reliable (static_cpu_has() is
>> already baked in), so clearing the cap won't flip rmpopt_capable(). The setup/enable split removes most of the if (rmpopt_wq)
>> checks anyway; the only one left is a single guard in snp_enable_rmpopt() for the (rare) allocation‑failure case, which I will
>> probably like to keep rather than rely on clearing the feature.
> 
> Or, you can introduce that bool rmpopt_enabled and clear it and test it in
> rmpopt_capable(). As long as it stays a static var, only visible in this
> compilation unit and not exported, that's good enough.
> 
>> I'll respin as v15 with the setup/enable split once we settle the feature‑clear question and the RMPOPT_BASE MSR programming
>> question (i.e., skipping it if RMPOPT_EN is already set).
> 
> Thx.
> 
> Btw, you can respin the last two patches only and send them as a reply to that
> thread - I have applied the first 3 already so no need to resend them again.
> 

One thing to sort out first, since you've already applied p1‑p3: the setup/enable rework reshapes a few things that landed
in p3 — snp_setup_rmpopt() becomes the single snp_enable_rmpopt() export, rmpopt_capable() now uses the rmpopt_enabled
guard, and the ccp caller in sev-dev.c changes with the rename. I can carry all of that as deltas in the respun p4 (i.e.
p3 adds snp_setup_rmpopt() and p4 renames/reworks it right after), but if you'd rather it land cleanly I can refresh p3
too so it introduces the final shape. Which would you prefer — p4 deltas over what's applied, or a refreshed p3 as well?

Thanks,
Ashish

  reply	other threads:[~2026-09-15 21:04 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-10 21:58 [PATCH v14 0/5] Add RMPOPT support Ashish Kalra
2026-09-10 21:59 ` [PATCH v14 1/5] x86/cpufeatures: Add X86_FEATURE_RMPOPT feature flag Ashish Kalra
2026-09-10 21:59 ` [PATCH v14 2/5] x86/sev: Disable CPU hotplug while SNP is active Ashish Kalra
2026-09-10 22:25   ` sashiko-bot
2026-09-10 22:46     ` Kalra, Ashish
2026-09-10 21:59 ` [PATCH v14 3/5] x86/sev: Initialize RMPOPT configuration MSRs Ashish Kalra
2026-09-10 22:00 ` [PATCH v14 4/5] x86/sev: Perform RMP optimizations asynchronously Ashish Kalra
2026-09-10 22:11   ` sashiko-bot
2026-09-10 22:40     ` Kalra, Ashish
2026-09-12  1:53   ` Borislav Petkov
2026-09-14 20:00     ` Kalra, Ashish
2026-09-14 23:15       ` Borislav Petkov
2026-09-15 21:04         ` Kalra, Ashish [this message]
2026-09-15 23:37           ` Borislav Petkov
2026-09-10 22:00 ` [PATCH v14 5/5] x86/sev: Re-enable RMP optimizations on SNP guest shutdown Ashish Kalra
2026-09-10 22:12   ` sashiko-bot
2026-09-10 23:10     ` Kalra, Ashish

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1c3d9841-eef8-4c94-9b2c-a7ed92a68260@amd.com \
    --to=ashish.kalra@amd.com \
    --cc=KPrateek.Nayak@amd.com \
    --cc=Michael.Roth@amd.com \
    --cc=Nathan.Fontenot@amd.com \
    --cc=Tycho.Andersen@amd.com \
    --cc=ackerleytng@google.com \
    --cc=aik@amd.com \
    --cc=ardb@kernel.org \
    --cc=babu.moger@amd.com \
    --cc=bp@alien8.de \
    --cc=darwi@linutronix.de \
    --cc=dave.hansen@linux.intel.com \
    --cc=davem@davemloft.net \
    --cc=dyoung@redhat.com \
    --cc=herbert@gondor.apana.org.au \
    --cc=hpa@zytor.com \
    --cc=jackyli@google.com \
    --cc=jacobhxu@google.com \
    --cc=kvm@vger.kernel.org \
    --cc=linux-coco@lists.linux.dev \
    --cc=linux-crypto@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=nikunj@amd.com \
    --cc=pawan.kumar.gupta@linux.intel.com \
    --cc=pbonzini@redhat.com \
    --cc=peterz@infradead.org \
    --cc=pgonda@google.com \
    --cc=rientjes@google.com \
    --cc=seanjc@google.com \
    --cc=tglx@kernel.org \
    --cc=thomas.lendacky@amd.com \
    --cc=x86@kernel.org \
    --cc=xin@zytor.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.