From: Paul Walmsley <pjw@kernel.org>
To: Andy Chiu <tchiu@tenstorrent.com>
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-riscv@lists.infradead.org, andybnac@gmail.com,
dfustini@oss.tenstorrent.com, greentime.hu@sifive.com,
daichengrong <daichengrong@iscas.ac.cn>,
Yong-Xuan Wang <yongxuan.wang@sifive.com>
Subject: Re: [PATCH v6 2/8] riscv: vector: refactor context switch for kernel-mode vector
Date: Tue, 6 Oct 2026 04:02:08 -0600 (MDT) [thread overview]
Message-ID: <1d9e4bf4-e057-f671-3285-c5613869ca56@kernel.org> (raw)
In-Reply-To: <20260918215154.2481482-3-tchiu@tenstorrent.com>
On Fri, 18 Sep 2026, Andy Chiu wrote:
> When context switching out a thread in preemptible kernel-mode vector,
> there are 2 distinct cases: One is voluntary switch and the other is
> trap-introduced switch. We don't need to save vector context for
> voluntary switch and the context is always !dirty as long as we clear
> the dirty bit at riscv_v_context_nesting_end().
>
> Signed-off-by: Andy Chiu <tchiu@tenstorrent.com>
Thanks, queued for v7.4.
- Paul
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next prev parent reply other threads:[~2026-10-06 10:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-18 21:51 [PATCH v6 0/8] riscv: optimize mode switch latency for Vector Andy Chiu
2026-09-18 21:51 ` [PATCH v6 1/8] riscv: do not read csr in vector context switch Andy Chiu
2026-10-06 10:01 ` Paul Walmsley
2026-09-18 21:51 ` [PATCH v6 2/8] riscv: vector: refactor context switch for kernel-mode vector Andy Chiu
2026-10-06 10:02 ` Paul Walmsley [this message]
2026-09-18 21:51 ` [PATCH v6 3/8] selftest: riscv: test vectorized user copy Andy Chiu
2026-09-18 21:51 ` Andy Chiu
2026-10-06 10:02 ` Paul Walmsley
2026-10-06 10:02 ` Paul Walmsley
2026-09-18 21:51 ` [PATCH v6 4/8] riscv: vector: refactor vector context operations Andy Chiu
2026-09-18 21:51 ` Andy Chiu
2026-09-18 21:51 ` Andy Chiu
2026-09-18 21:51 ` [PATCH v6 5/8] riscv: clarify vector state semantics on syscall and context switch Andy Chiu
2026-09-18 21:51 ` [PATCH v6 6/8] riscv: vector: adjust ptrace and signal behavior for INITIAL state Andy Chiu
2026-09-18 21:51 ` [PATCH v6 7/8] selftests: riscv: Extend vector tests for sigreturn and ptrace Andy Chiu
2026-09-18 21:51 ` Andy Chiu
2026-09-18 21:51 ` [PATCH v6 8/8] riscv: vector: optimize vstate operations Andy Chiu
2026-09-18 21:51 ` Andy Chiu
2026-10-06 9:40 ` [PATCH v6 0/8] riscv: optimize mode switch latency for Vector patchwork-bot+linux-riscv
2026-10-07 14:20 ` Paul Walmsley
2026-10-06 10:01 ` Paul Walmsley
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