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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <975b6883-646d-4db4-b931-b21c45d0507b@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1774522966-4B04472C-CD4C0261/0/0 X-purgate-type: clean X-purgate-size: 2005 On 26.03.2026 11:35, Tu Dinh wrote: > On 26/03/2026 11:21, Teddy Astie wrote: >> Add all CPU models that supports these MSR as they are defined in February 2026 SDM. >> It uses the same list that span from Skylake to latest CPU models as a part of >> >> MSRs in the 6th—13th generation Intel® Core™ processors, >> 1st—5th generation Intel® Xeon® Scalable processor families, >> Intel® Core™ Ultra 7 processors, 8th generation Intel® Core™ i3 >> processors, Intel® Xeon® E processors, Intel® Xeon® 6 P-Core >> processors, Intel® Xeon® 6 E-Core processors, and Intel® Series 2 >> Core™ Ultra processors >> >> Signed-off-by: Teddy Astie >> --- >> Currently, none of these MSR are exposed on these CPUs, leading to BSOD [1] >> in Windows when it is supposedly trying to debug some program. >> >> I guess [2] is also caused by these missing MSRs. >> >> [1] https://xcp-ng.org/forum/topic/12008/application-on-vm-causing-bsod >> [2] https://lore.kernel.org/xen-devel/ced16fca-3b55-40a1-a7e2-ffadd9707394@vates.tech/ >> >> xen/arch/x86/hvm/vmx/vmx.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> > > I don't think CPU models with architectural LBRs should be stuffed > together with the model-specific ones instead of having their own case. I agree. We want to at least determine (or even enforce) how many LBRs are accessible. After all we can't be sure the DEPTH field hasn't been altered before we gained control. Beyond that, because arch-LBR enabling is a significant effort, I guess using the existing machinery for the time being might be okay. > With that said, short of fully implementing arch LBR, it might make > sense to at least stub out the LER MSRs to allow Windows to read them > without crashing, as certain versions of Windows use LER MSR indexes > without checking the arch LBR CPUID bit. This would be too Windows-centric for my taste. Jan