From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/6] drm/i915: Clean up gen2 DPLL readout
Date: Tue, 19 Mar 2019 13:34:31 +0000 [thread overview]
Message-ID: <1f079235-794d-45ec-e57d-688c5ce4ef3a@linux.intel.com> (raw)
In-Reply-To: <20190318165633.28924-6-ville.syrjala@linux.intel.com>
On 18/03/2019 16:56, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The current gen2 DPLL readout code:
> * assumes i845/i865 have LVDS which is not true
> * assumes only pipe B can drive LVDS (true, but makes
> the code appear a bit magical)
> * hard to parse in general
>
> Clean it up by checking for i85x (the only gen2 platform
> with LVDS) and reusing intel_lvds_port_enabled().
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2ba61181746d..9f31d94fc04b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10809,7 +10809,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int pipe = pipe_config->cpu_transcoder;
> u32 dpll = pipe_config->dpll_hw_state.dpll;
> u32 fp;
> struct dpll clock;
> @@ -10858,10 +10857,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> else
> port_clock = i9xx_calc_dpll_params(refclk, &clock);
> } else {
> - u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
> - bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
> + enum pipe lvds_pipe;
> +
> + if (IS_I85X(dev_priv) &&
> + intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
> + lvds_pipe == crtc->pipe) {
> + u32 lvds = I915_READ(LVDS);
>
> - if (is_lvds) {
> clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
> DPLL_FPA01_P1_POST_DIV_SHIFT);
>
>
I defer to domain experts on this one.
Regards,
Tvrtko
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next prev parent reply other threads:[~2019-03-19 13:34 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-18 16:56 [PATCH 1/6] drm/i915: Reorder gen3/4 swizzle detection logic Ville Syrjala
2019-03-18 16:56 ` [PATCH 2/6] drm/i915: Introduce i9xx_has_pfit() Ville Syrjala
2019-03-19 13:24 ` Tvrtko Ursulin
2019-03-19 14:14 ` Ville Syrjälä
2019-03-19 14:23 ` [PATCH v2 " Ville Syrjala
2019-03-20 7:19 ` Tvrtko Ursulin
2019-03-18 16:56 ` [PATCH 3/6] drm/i915: Introduce i9xx_has_pps() Ville Syrjala
2019-03-19 13:26 ` Tvrtko Ursulin
2019-03-18 16:56 ` [PATCH 4/6] drm/i915: Introduce i915_has_asle() Ville Syrjala
2019-03-19 13:27 ` Tvrtko Ursulin
2019-03-18 16:56 ` [PATCH 5/6] drm/i915: Use HPLLVCO_MOBILE for all PNVs Ville Syrjala
2019-03-19 13:29 ` Tvrtko Ursulin
2019-03-20 15:27 ` Ville Syrjälä
2019-03-18 16:56 ` [PATCH 6/6] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2019-03-19 13:34 ` Tvrtko Ursulin [this message]
2019-03-19 14:17 ` Ville Syrjälä
2019-03-18 23:35 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection logic Patchwork
2019-03-19 13:06 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-19 13:15 ` [PATCH 1/6] " Tvrtko Ursulin
2019-03-19 15:50 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection logic (rev2) Patchwork
2019-03-20 0:40 ` ✓ Fi.CI.IGT: " Patchwork
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