[MODERATED] Re: [patch V9 00/16] SSB

[Tim Chen <tim.c.chen@linux.intel.com>]

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On 05/01/2018 08:24 AM, speck for Thomas Gleixner wrote:
> Changes vs. V8:
> 
> Addressed review feed back and added Linus variant of
> alternative_write_msr().
> 
>  - Use EINVAL in the prctl
> 
>  - Fix the sbb typos
> 
>  - Make AMD default to prctl as well (Borislav)
> 
>  - Add the not affected CPU types (Tim)
> 
> I've updated the git repository as well
> 
>   ssh://git@cvs.ou.linutronix.de/linux/speck/linux master (forced update)
> 
> There are also two stable backport branches now:
> 
>   ssh://git@cvs.ou.linutronix.de/linux/speck/linux linux-4.16.y
> 
>   ssh://git@cvs.ou.linutronix.de/linux/speck/linux linux-4.14.y
> 
> 
> Delta patch against V8 below. Git bundle against 4.17-rc3 follows in
> separate mail.
> 
> Thanks,
> 
> 	tglx
> 

This version also has a bug that's in the v8 patch.  For whole platform
disabling of speculation, only CPU 0 has RDS enabled.

root@otc-cfl-s-02:~# cat /sys/devices/system/cpu/vulnerabilities/spec_store_bypass 
Mitigation: Speculative Store Bypass disabled

msr 0x48 cpu 0  val: 4
msr 0x48 cpu 1  val: 0
msr 0x48 cpu 2  val: 0
msr 0x48 cpu 3  val: 0
msr 0x48 cpu 4  val: 0
msr 0x48 cpu 5  val: 0
msr 0x48 cpu 6  val: 0
msr 0x48 cpu 7  val: 0
msr 0x48 cpu 8  val: 0
msr 0x48 cpu 9  val: 0
msr 0x48 cpu 10  val: 0
msr 0x48 cpu 11  val: 0

I used the fix below to take care of Intel CPU. The fix also works for
CPU taken offline and back online.  AMD cpu has the proper setting
of their MSR in boot up via identify_secondary_cpu's call to
x86_setup_ap_spec_ctrl.

void x86_setup_ap_spec_ctrl(void)
{
        if (boot_cpu_has(X86_FEATURE_IBRS))
                x86_set_spec_ctrl(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);

        if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
                x86_amd_rds_enable();
}

But AMD cpu may have issue when CPU is brought offline and back online as
x86_setup_ap_spec_ctrl may not get called then.

Tim

---

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ef3f9c0..c799e48 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -770,6 +770,9 @@ static void init_intel(struct cpuinfo_x86 *c)
 	init_intel_energy_perf(c);
 
 	init_intel_misc_features(c);
+
+	if (cpu_has(c, X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+		x86_set_spec_ctrl(SPEC_CTRL_RDS);
 }
 
 #ifdef CONFIG_X86_32