Re: [parisc-linux] lasi scsi driver

[Jerry Huck <jerry_huck@hp.com>]

> From: "Gyula Matics" <gyula_matics@hp.com>
> To: <parisc-linux@puffin.external.hp.com>
> Date: Thu, 2 Mar 2000 21:42:50 +0100
> Subject: [parisc-linux] lasi scsi driver

> It's only half working. It can list the devices on the bus, but that's all.
> 
> It is not working because it needs a horrible amount of cache flushing
> and I still didn't get it right. (the committed code only contains enough
> flushing to pass the two debugging tests)
> 
> The scsi card is running code that is in the main memory and the driver
> is heavily patching that. The bigger problem is that the communication
> with the card is done via a mailbox also residing in the main memory
> and the driver is assuming that this mailbox is on a non-cacheable page.
> 
> I know that the architecture supports setting a page non-cacheable.
> My question is if it is possible / good idea to set the mailbox page
> to non-cacheable?
> 
> Gyula

While the PA-RISC processor architecture supports the notion of a
non-cacheable page, most HP memory systems do not - certainly not the
most recent memory systems.  If you set the U-bit on a main memory page
and then reference the page, the processor will emit a sub-cacheline
transaction and the memory system will do something bad (probably
HPMC).  Also, I can't find any architected interface that would let
you test if a memory page could be accessed uncacheable.

Even for IA-64, main memory systems do not have to support uncacheable
references.  A PDC-like mechanism - PAL/SAL/EFI - reports the
available memory ranges and gives the supported attributes.  In the
IA-64 case, the I/O system is coherent so you don't need any of the
cache flushing.  So don't ever get in the situation where you need
uncacheable main memory.

Jerry Huck