From: Ralf Baechle <ralf@oss.sgi.com>
To: Jun Sun <jsun@mvista.com>
Cc: "Kevin D. Kissell" <kevink@mips.com>,
linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr
Subject: Re: PROPOSAL : multi-way cache support in Linux/MIPS
Date: Thu, 3 Aug 2000 01:31:55 +0200 [thread overview]
Message-ID: <20000803013155.A2097@bacchus.dhis.org> (raw)
In-Reply-To: <3988AA72.5C342E1D@mvista.com>; from jsun@mvista.com on Wed, Aug 02, 2000 at 04:10:43PM -0700
On Wed, Aug 02, 2000 at 04:10:43PM -0700, Jun Sun wrote:
> > So, to get back to Linux, a MIPS32 part can *almost*
> > run the standard MIPS R4K kernel. Almost. What had
>
> Still one more question. If I understand correctly, the 4Km and 4Kp are
> MIPS32 CPUs. However, they don't have TLBs. Right? Without TLBs, I
> don't suppose Linux will run ...
There is ``Microcontroller Linux'' aka uclinux available at www.uclinux.org.
It could be ported to TLB-less processors. You'd loose some of the
important functionality of the standard Linux, including some source
compatibility.
Ralf
next prev parent reply other threads:[~2000-08-02 23:35 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-08-02 22:44 PROPOSAL : multi-way cache support in Linux/MIPS Kevin D. Kissell
2000-08-02 22:44 ` Kevin D. Kissell
2000-08-02 23:10 ` Jun Sun
2000-08-02 23:31 ` Ralf Baechle [this message]
-- strict thread matches above, loose matches on Subject: below --
2000-08-02 18:36 Kevin D. Kissell
2000-08-02 18:36 ` Kevin D. Kissell
2000-08-02 18:15 Kevin D. Kissell
2000-08-02 18:15 ` Kevin D. Kissell
2000-08-02 21:50 ` Jun Sun
2000-08-02 8:26 Kevin D. Kissell
2000-08-02 8:26 ` Kevin D. Kissell
2000-08-02 17:05 ` Jun Sun
2000-08-01 23:52 Jun Sun
2000-08-02 18:12 ` Dominic Sweetman
2000-08-02 21:38 ` Jun Sun
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