From: acmay@acmay.homeip.net
To: jpeters@mvista.com
Cc: andrew may <acmay@acmay.homeip.net>,
John Tyner <jtyner@cs.ucr.edu>,
linuxppc-commit@source.mvista.com,
linuxppc-embedded@lists.linuxppc.org
Subject: Re: ppc405 enet changes (fwd)
Date: Wed, 5 Sep 2001 09:25:36 -0700 [thread overview]
Message-ID: <20010905092536.C621@sink.san.rr.com> (raw)
In-Reply-To: <3B9632EB.51904875@mvista.com>; from jpeters@mvista.com on Wed, Sep 05, 2001 at 07:12:59AM -0700
On Wed, Sep 05, 2001 at 07:12:59AM -0700, jpeters@mvista.com wrote:
> In addition, many of the embedded system boards around are still
> not what you would call blindingly fast. The 405 chips I had would
> do a maximum of 200 Mhz and the additional software cache
> coherency code made it look a lot slower. In a situation like
> this anything to reduce instruction count speeds up execution.
> Especially if it is code that runs at interrupt level.
So did you chose the vars that were to be static and the ones in
dev->priv for speed? If so it would be nice to see how you decided
which ones when where.
I would think that it would be best to keep all the vars as close
together in mem as possible, to keep them on the fewest number of
cache-lines. By splitting them between two sections I would think
it hurts more than it helps.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
prev parent reply other threads:[~2001-09-05 16:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <Pine.LNX.4.30.0109031513110.21186-200000@hill.cs.ucr.edu>
[not found] ` <20010903202915.A25163@cpe-24-221-152-185.az.sprintbbd.net>
2001-09-04 20:07 ` ppc405 enet changes (fwd) andrew may
[not found] ` <3B9557CA.D76C70E2@mvista.com>
2001-09-04 22:26 ` andrew may
2001-09-05 0:06 ` Dan Malek
[not found] ` <20010904180915.E14548@ecam.san.rr.com>
2001-09-05 2:39 ` Tom Rini
[not found] ` <3B9632EB.51904875@mvista.com>
2001-09-05 16:09 ` acmay
2001-09-05 16:25 ` acmay [this message]
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