[PATCH] Pentium IV cacheline size.

[Dave Jones <davej@suse.de>]

Currently, we're using a L1_CACHE_SHIFT value of 7
for Pentium 4, which equates to 128 byte cache lines.
Curious, I dumped the info on the only P4 I could find,
and noticed they were 64 byte.
Upon checking the documentation, they're 64 byte there too. 
Is this just a thinko on someones part, or was there a
rationale behind this that I've not realised ?

If it is wrong, patch below sets it back to 64 bytes.

regards,

Dave.


diff -urN --exclude-from=/home/davej/.exclude linux/arch/i386/config.in linux-dj/arch/i386/config.in
--- linux/arch/i386/config.in	Fri Oct 12 16:29:57 2001
+++ linux-dj/arch/i386/config.in	Sat Oct 13 12:40:19 2001
@@ -108,7 +108,7 @@
    define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
 fi
 if [ "$CONFIG_MPENTIUM4" = "y" ]; then
-   define_int  CONFIG_X86_L1_CACHE_SHIFT 7
+   define_int  CONFIG_X86_L1_CACHE_SHIFT 6
    define_bool CONFIG_X86_TSC y
    define_bool CONFIG_X86_GOOD_APIC y
    define_bool CONFIG_X86_PGE y

-- 
| Dave Jones.                    http://www.codemonkey.org.uk
| SuSE Labs .