Re: [PATCH] PCI updates - 32-bit IO support

[Russell King <rmk@arm.linux.org.uk>]

On Wed, Dec 19, 2001 at 09:30:19PM -0800, David S. Miller wrote:
> Don't the PCI specs actually talk about 24-bits in fact?
> 
> Russell does you box really have the full 32-bits or is it
> really just 24-bits?

Shrug - the chip documentation isn't good enough to indicate either.

What I do know is:

- setting the bridge and eepro100 up with 16-bit IO addresses causes PCI
  master aborts.
- setting the bridge and eepro100 up with 32-bit IO addresses which
  correspond to the host MMIO region, it works perfectly.

It appears that the first bridge converts the mmio access into a PCI
IO read/write cycle without any address translation.  So, when I
access mmio 0x90011000, it would appear to cause a PCI IO cycle at
the same address.

The MMIO region for this bus is 0x90010000 - 0x9001ffff, so its impossible
to test the effect of different upper 16-bits.

I suppose I could waste some time by getting Linux to generate lots of IO
cycles and scoping the PCI bus lines to find the PCI address, but I think
its rather academic in light of the above.

--
Russell King (rmk@arm.linux.org.uk)                The developer of ARM Linux
             http://www.arm.linux.org.uk/personal/aboutme.html