From: Jun Sun <jsun@mvista.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: ralf@oss.sgi.com, linux-mips@oss.sgi.com
Subject: Re: [PATCH] disable interrupt for non-LLSC atomic set
Date: Fri, 11 Jan 2002 09:23:46 -0800 [thread overview]
Message-ID: <20020111092346.C32345@mvista.com> (raw)
In-Reply-To: <Pine.GSO.3.96.1020111115109.11015A-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Fri, Jan 11, 2002 at 11:54:24AM +0100
On Fri, Jan 11, 2002 at 11:54:24AM +0100, Maciej W. Rozycki wrote:
> On Thu, 10 Jan 2002, Jun Sun wrote:
>
> > The current MIPS_ATOMIC set code for no-LLSC case does a load and store with
> > interrupt open. This is potentially dangerous as an interrupt could happen
> > in-between and cause the value changed inside the interrupt handler.
>
> No need to -- no sane interrupt handler will ever access a user's atomic
> variable.
>
OK, I have to reveal the secret desire :-). I have a patch
that makes MIPS kernel preemptible, and that unprotected operation
becomes very volunerable with the preemptible patch.
Jun
next prev parent reply other threads:[~2002-01-11 18:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-01-11 1:53 [PATCH] disable interrupt for non-LLSC atomic set Jun Sun
2002-01-11 10:54 ` Maciej W. Rozycki
2002-01-11 17:23 ` Jun Sun [this message]
2002-01-11 17:40 ` Maciej W. Rozycki
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